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Asynchronous WISHBONE-compatible SDRAM controller: Overview Details Name: yadmc Created: 01-Aug-2008 21:09:22 Updated: 09-Nov-2008 18:15:15 CVS: browse Other project properties Category :: Memory core Language :: Verilog License :: GPL Phaze :: FPGA proven Standard :: Wishbone compliant core Development status :: Production/Stable Project maintainers Sebastien Bourdeauducq Statistics view Description Sequential SDR SDRAM controller with direct mapped cache and separated SDRAM clock domain. Features WISHBONE compatible. System and SDRAM clocks can be different. No frequency or phase relationship required. High frequency SDRAM operation: 100MHz on XC3S1200E-4 with default synthesis options. Supports 16-bit PC133 SDR SDRAM (defaults parameters are for Micron MT48LC16M16A2-7E, if using a different chip some modifications may be needed). Can be easily modified for DDR or other bus widths. Direct mapped cache (configurable size) enabling burst SDRAM transfers. WISHBONE bursts and SDRAM prefetchs to the cache are not implemented. Status Hardware proven on the OMRP (www.openpattern.org).