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SystemC USB1.1 IP Core: Overview Details Name: usb11 Created: 10-May-2004 18:55:08 Updated: 09-Jul-2004 17:01:15 CVS: browse Other project properties Category :: Communication controller Language :: Other Phaze :: Design done Development status :: Production/Stable Project maintainers Alfredo Luiz Foltran Fialho Statistics view Description This project consists of the translation of the USB 1.1 Function IP Core Verilog code and dependencies, maintained by Rudolf Usselmann, into a Synopsys CoCentric SystemC Compiler compatible SystemC code. This project is part of the BrazilIP Fenix project. Features Written In SystemC Synopsys CoCentric SystemC Compiler Compatibility Fully Synthesisable 8051 Interface OCP Interface Test bench is included SystemC code: simulation through binary generated by the gcc Verilog code: simulation through tools like ModelSim or Icarus (the IP Core Verilog files may be generated by CoCentric SystemC Compiler) Status The translation is done. It was verified by simulation with OCP Interface (SystemC and Verilog.) It was verified by simulation with 8051 Interface (Verilog.) OCP Interface Protocol under verification. The hardware verification will be made (XILINX XC2V2000.) The XILINX TIMED SIMULATION (Verilog code generated by ISE) in ModelSim is done.   Requirements SystemC v2.0.1 g+ or Visual C++ Compilers Synopsys CoCentric SystemC Compiler (optional)