Overview :: News :: Downloads :: Tracker :: Discussions (cores) :: CVS

OPB SPI Slave : Overview Details Name: spi_slave Created: 19-Nov-2007 21:21:37 Updated: 15-May-2008 21:57:02 CVS: browse Other project properties Category :: Communication controller Language :: VHDL License :: LGPL Phaze :: FPGA proven Development status :: Production/Stable Project maintainers Daniel Koethe Statistics view Description The OPB SPI Core connects a FPGA to a DSP or Microprocessor as Slave-Device. This means all transfers are initiated by the Master an the FPGA-System only responds to read or write request. Features OPB-Clock and SPI-Clock are complete independent SPI can run faster than OPB if guaranteed that no TX-FIFO Underrunn or RX- FIFO Overrunn occure. variable transfer length 2..32 Automatic CRC-Generation for Transmit and Receive Data (only 8,32Bit Shift-Register Width) Status simulation tests done Hardware tests on a Virtex-4 ML401 Board (LX25) done CRC-Code Real World Test in progress