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SardMIPS: Overview Details Name: sardmips Created: 21-Jan-2006 03:04:46 Updated: 09-Feb-2006 16:39:38 CVS: browse Other project properties Category :: Microprocessor Category :: SoC Language :: Other License :: GPL Development status :: Alpha Project maintainers Igor Loi Statistics view Embedded MIPS R2000 It's a synthesizable parametric IP core of 32 bit RISC processor supporting full MIPS R2000 ISA, by using SystemC HDL. An optional CP0 coprocessor implementing full exception handling was also modelled. Also 64 bit pipeline multiplier supporting is optional, and pipeline depth is configurable. Features feature1 feature1.1 -feature1.2-feature2 Status Some bugs was fix. -> correct bug when intterupt occur during MFLO and MFHI instruction. Now I'm working on the CP0 status 2