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kiss-board: Overview Details Name: kiss-board Created: 28-May-2006 20:30:58 Updated: 24-Jul-2008 11:55:58 CVS: browse Other project properties Category :: Prototype board Category :: SoC Development status :: Production/Stable Project maintainers hirotaka fukuchi Statistics view Description BOARD consists of two pieces. One is FPGA board. Another is MOTHER board. The device on the FPGA board is ANY(xilinx or altera ...).Only connected specification of the board is important. Specification [Keep It Simple,Stupid] Board. The board was evaluated like [or1k/orp project]. Status Assembly It's planning(more cheap!) Evaluation It's continuance(commit code,RTL8019AS Evaluation is done) Simulation It's finished(commit code,checkout-test is done) Design It's finished(commit code,checkout-test is done) Assembly Board is not available(Not yet).so the evaluation doesn't end completely... More Information Board Specification(Only japanese langage) -- It is stopping now. so sorry! :) If you have a question,you can contact us,please refer to following web-page. Provider<-may be(Only japanese langage) Formmail(Only japanese langage) TODO Reduce cost This is Expensive or Cheap? How to do?(thinking) The examination point is put out. How is the Debug-Interface-pin? This WEB page is maintained Add Board electrical information Add Teaching material information Design Hardware PCB architecture Board name pdf-file Connector pdf-file Circuit of mother board(As reference) pdf-file Circuit of fpga board(As reference) pdf-file SOC architecture OR1200 block(As documentation,please Refer [OpenRisc 1000] project) pdf-file System hierarchy pdf-file System block pdf-file Software(Under construction) Compiler(HowTo) binutils(Under construction) gcc(Under construction) linker(HowTo) section Section Usage .reset InstractionCode at Start .vectors InstractionCode at Exception .text InstractionCode(normal) .icm InstractionCode(early) .data DataCode(initialization) .bss DataCode(no-initialization) .extdata ExtendDataCode(initialization) .extbss ExtendDataCode(no-initialization) .stack StackArea memory Device Address Usage InternalSRAM0 0x00000000 Exception InternalSRAM1 0x01000000 NotImpliment ExternalSDRAM0 0x02000000 --- ExternalSDRAM1 0x03000000 VRAM ExternalFlash 0x03000000 BIOS ld script(Under construction) function(As Example) interrupts Core Locate Exception Interface TickTimer OpenRisc1000(OR1200) 0x500 Internal UART16550 SOC-Peripheral 0x800 WishBone WB_DMA SOC-Peripheral 0x800 WishBone function hierarchy pdf-file syscall(As Example) wrapper(Under construction) Simulation How to simulate? ModelSim with PseudoScreen(pan-popen-PLI and ram-screen) Screenshot Procedure(Under construction) Evaluation Benchmark Program code Outline Draw1:Normal render(Read,Write) Draw2:RGB565->YUV,Y:modulation,YUV->RGB565(Read,Calculation,Write) Erase:Clear VRAM(Write) Sytem Condition Case 1:CPU=25MHz,WB=25MHz,EXT_MEM=50MHz Case 2:CPU=30MHz,WB=30MHz,EXT_MEM=50MHz Case 3:CPU=25MHz,WB=25MHz,EXT_MEM=60MHz OR1200 Condition Case A:IC=no-used,DC=no-used Case B:IC=4KByte ,DC=no-used Case C:IC=no-used,DC=4KByte Case D:IC=4KByte ,DC=4KByte MISC condition VramRenderRoutine on EXT_FLASH[.text section](include Cache) InterruptsHandler on QMEM[.icm section] ImageDataSize(40x50pixel) is 4000byte(include Cache) The byte_order of QMEM is enable. Demonstration phots All Connector Draw1Test Draw2Test Results Draw1Test Draw2Test Erase Board snapshots MOTHER board TopView BottomView FPGA board TopView BottomView