LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Overview :: News :: Downloads :: Tracker    

    IrDA: Overview

    Details

    Name: irda
    Created: 25-Sep-2001 10:15:03
    Updated: 26-Aug-2002 17:20:13
    CVS: browse

    Other project properties

    Category :: Communication controller
    Standard :: Wishbone compliant core
    Development status :: Production/Stable

    Project maintainers

  • Jacob Gorban
  • Statistics

  • view
  • Description

    IrDA core that utilizes uart16550 core for 115.2Kbit/s IrDA communication. Required bit encoding/decoding is performed.
    The 115.2 (SIR) mode should work alright.

    There's also a lot of code for MIR and FIR, much faster communication modes. Yet they are not fully tested and are sure to contain a lot of bugs.

    Features

    • Designed for all standard IR transceivers.
    • Implements WISHBONE bus interface
    • Up to 4Mbit communication speed
    • Programmable clock selection
    • Loopback option for testing
    • Works with WISHBONE bus clock
    • Can request DMA transfers

    Status

    Currently, only 115.2 (SIR) mode is done well. Use irda_top_sir_only.v top-level module.
    Faster modes (MIR, FIR) are not tested well but the specs and most of the code for them exist, just not tested and debugged well.


     

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.