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I2S Interface: Synthesis FPGA Synthesis results Resource utilization for the I2S Interface is shown below for two popular FPGA targets. Exact numbers will depend on tool used, tool settings and target architecture. Receiver I2S Receiver Altera Cyclone Xilinx Spartan 3 Slave mode: DATA_WIDTH = 32 ADDR_WIDTH = 5 189MHz 267 LE's 0,512kbit ram 110MHz 160 slices 18,432kbit ram Master mode: DATA_WIDTH = 32 ADDR_WIDTH = 5 167MHz 299 LE's 0,512kbit ram 90MHz 183 slices 18,432kbit ram Transmitter I2S Transmitter Altera Cyclone Xilinx Spartan 3 Slave mode: DATA_WIDTH = 32 ADDR_WIDTH = 5 144MHz 153 LE's 0,512kbit ram 105MHz 92 slices 18,432kbit ram Master mode: DATA_WIDTH = 32 ADDR_WIDTH = 5 124MHz 238 LE's 0,512kbit ram 90MHz 114 slices 18,432kbit ram