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Generic FIFOs: Overview Details Name: generic_fifos Created: 24-Sep-2002 22:10:22 Updated: 11-Feb-2004 08:39:00 CVS: browse Other project properties Category :: Memory core Language :: Verilog Phaze :: FPGA proven Development status :: Production/Stable Project maintainers Rudolf Usselmann Statistics view Description Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are parameterizable and use generic_memories for memory. These FIFOs are fully portable from FPGAs to ASICS. Features Written in Verilog Fully Synthesizable (FPGA & ASIC libraries) Parameterized Single and Dual Clock Status All FIFOs that are release are done. They have been simulated and most of them have been used in one way or another in one of my projects. Some have been verified in real hardware. October 2003, Added a dual clock FIFO that is gray code encoded (fully parameterizable) Dependencies To use this IP core, you must also download the generic memories models. This IP Core is provided by: www.ASICS.ws - Solutions for your ASIC/FPGA needs -