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Floating Point Unit: Overview
Description
This is a single precision floating point unit. It is fully IEEE 754 compliant. It can currently perform Add/Sub, Mul and Divide operations, as well as integer to floating point and floating point to integer conversions. It supports four rounding modes: Round to Nearest Even, Round to Zero, Round to +INF and Round to -INF. There is now also a separate FP compare unit. It is located in the fpu/fcmp directory.
Motivation
- A 100% IEEE 754 compliant Floating Point Unit
- Usable by the OR1K CPU
- Options to extend the core
- Free !
Compatibility
To the best of my knowledge the FPU is 100% IEEE 754 compliant. I have run over 14Mil. test vectors on it, that where generated using the SoftFloat library by John R. Hauser, which can be found at: http://www.jhauser.us/arithmetic/SoftFloat.html.
The test pattern generator is included with the distribution.
Performance
- Single cycle execution
- 4 stage pipeline
Implementing the core
It is very difficult to partition such a complex piece of hardware for optimal pipe lining. Therefore you will need a synthesis tool that has a "retiring" feature to obtain best results. Actual Add/Sub, Multiply and Divide cores must be replaced in the primitives.v file, or your synthesis tool must be able to synthesize them for you. I might fix this in the future.
Status
- Second version of the core is released. Included with the release is also a test bench and a test pattern generator.
- I won't be doing any more work on the core in the near future, except for bug fixes.
- The core can be downloaded from OpenCores CVS via cvsweb or via cvsget (use fpu for module name)
Things that need to be done
- Add a remainder function
- Predict leading zeros to improve performance of post normalize unit
Change log
- 9/16/00 RU Added FP compare unit
- 9/15/00 RU Added int to float and float to int conversion
- 9/15/00 RU Fixed documentation
- 9/13/200 RU Initial release
This IP Core is provided by:
www.ASICS.ws - Solutions for your ASIC/FPGA needs -
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