Overview :: News :: Downloads :: Tracker

CF Floating Point Multiplier: Overview Details Name: cf_fp_mul Created: 13-Mar-2003 18:42:30 Updated: 08-May-2008 08:30:14 CVS: no files in cvs Other project properties Category :: Arithmetic core Development status :: Production/Stable Project maintainers Tom Hawkins Statistics view Description Cores are generated from Confluence; a modern logic design language. Confluence is a simple, yet highly expressive language that compiles into Verilog, VHDL, and C. See Confluent for more info. Features The floating point representation follows the IEEE-754 bit format: {SignBit, Exponent, Mantissa} Each file is stand-alone and represents a specific configuration. The 3 configuration parameters are: Combinatorial or Pipelined ('c' or 'p') Exponent Precision Mantissa Precision Note the total width = 1 + Exponent Precision + Mantissa Precision. For pipeline configurations, pipeline latency is 4 + Mantissa Precision. The configuration parameters are coded in the file name. For example, cf_fp_mul_p_11_52 has the following configuration: Pipelined 11-Bit Exponent 52-Bit Mantissa Current configurations: cf_fp_mul_c_3_4 cf_fp_mul_p_3_4 cf_fp_mul_c_5_10 cf_fp_mul_p_5_10 cf_fp_mul_c_8_23 (IEEE-754 Single) cf_fp_mul_p_8_23 (IEEE-754 Single) cf_fp_mul_c_11_52 (IEEE-754 Double) cf_fp_mul_p_11_52 (IEEE-754 Double)