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ahb system generator: Overview
| Details Name: ahb_system_generator
Created: 23-Sep-2004 10:51:02
Updated: 02-Nov-2007 14:38:48
CVS: browse Other project properties Category :: SoC
Language :: VHDL
Phaze :: Design done
Development status :: Production/Stable
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Features
- AMBAtm specification compliant (rev 2.0)
- unified approach to multi-layer, lite and full amba systems
- programmable arbiter
- "template" master with programmable internal fifo and read/write latencies
- "template" slave with simple default behaviour (i.e. no "split/retry" responses)
- GUI for start-up
- testbench generation specific to the created system
- check of connection correctness
Description
The intention is to provide an easy way to configure, create and simulate a "complete" AHB system. The main block is the "AHB matrix", in which every declared master has to be connected to one or more slaves. In order to test the connectivity of the matrix, and to evaluate performance tradeoffs between different architectural choises a configurable arbitration scheme and a "template" model of a parametrizable master and slave are provided. A complete testbench is also available to test the main write and read accesses made by every master to the slaves mapped on its address space. AHB system generator is a script which builds via GUI or file all .vhd files required to
simulate the system: masters, slaves, arbiters, decoders, master and slave muxes. To run the AHB system generator you must have installed PERL and a GUI PERL module called Tk (see for example http://www.cpan.org/). This configurator is provided by www.ipdesign.eu
Available on request:
- Slave with "retry" behaviour with internal fifo
- Slave with "split" behaviour with internal fifo
- APB slave (simple memory-like interface)
More IPs on www.ipdesign.eu:
- AHB/AHB bridge
- AHB/APB bridge
- AHB DMA
- WB/AHB bridge
Other project properties
Category :: SoC
Language :: VHDL
License :: LGPL
Development status :: Production/Stable
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