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a VHDL 16550 UART core: Overview Details Name: a_vhd_16550_uart Created: 17-Feb-2006 17:45:28 Updated: 22-Jul-2008 02:27:05 CVS: no files in cvs Other project properties Category :: Communication controller Dependencies :: Other cores Language :: VHDL Phaze :: Design done Development status :: Production/Stable Project maintainers Howard A. LeFevre Statistics view Description A UART that is compatible with the industry standard 16550D Includes wrappers for the Wishbone and AMBA APB busses To down load library, click on "Downloads" on the tool bar, top of this page. Features Uses parts from the gh_vhdl_library project (3.17 or later) Sticky parity is not supported FIFO's are always enabled Status Design is finished 18 Jun 2007 P. Azkarate's addition of range for integers in Rx, Tx modules this helps when using the Altera tools 12 July 2007 fix a couple problems found by Matthias Klemm with 5, 6, and 7 bit transfers 14 July 2007 Correct FCR bit 3 information (DMA Mode control) 4 Aug 2007 fix some TOI problems 18 Aug 2007 add stopB to sensitivity list in TX module (works the same, but removes warning) 12 Oct 2007 fixed the bug reports (dated 10/11 Oct 2007) THRE Interrupt will now be generated when trans FIFO is empty and interrupt enable bit changes from disabled to enabled. (note on THRE operation added par 3.3) The Receiver Line Status Interrupt is cleared as suggested by Matthias Klemm (note to bug report dated 10/12/07) (mod to this fix 13 oct 2007) 21 July 2008 mod equ for iBreak_ITR, as suggested by Nathan Z.