Software Aided Wishbone Extension for Xilinx (R) PicoBlaze (TM) :: Overview
Project maintainers
Details
Name: wb4pb
Created: Jan 5, 2010
Updated: Feb 20, 2010
SVN Updated: Feb 20, 2010
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Processor
Language: VHDL
Development status: Stable
Additional info:
none
WishBone Compliant: Yes
License: BSD
Description
This project provides interface logic and assembler routines, giving PicoBlaze (TM) embedded soft-uC the ability to access wishbone systems or slave cores as an 8-bit master device. There is no native hardware handshake mechanism at PicoBlaze (TM) ports, so wishbone wait-state recognition is done by software polling. Some standard wishbone slave peripherals like GPIO and UART are included as well.
Features
- Multi HDL language implementation VHDL and Verilog (R)
- Assembler subroutines
- Simulation testbench and command file
- Notepad++ custom syntax highlighter for assembler
- Synthesizable GPIO example
- Synthesizable UART example, using Xilinx (R) UART macros together with a wishbone slave wrapper
- Baud rate calculation script
Getting Started
- Prerequisites: Xilinx ISE (R) and ModelSim Xilinx Edition III (R)
- Download wb4pb sources and be sure to keep directory structure!
- Download PicoBlaze (TM) from Xilinx (R) (registration required)
- Copy kcpsm3.v and kcpsm3.vhd to rtl directory
- Open picoblaze_wb_gpio_tb.do in a text editor and customize "set wd ..." and "set isVHDL ..." lines
- Start ModelSim (R) and execute DO-File (Menu->Tools->TCL->Execute Macro...)