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Details

Name: aes_crypto_core
Created: Dec 7, 2004
Updated: Dec 20, 2009
SVN Updated: No data
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Crypto core
Language: VHDL
Development status: Stable
Additional info: Design done
WishBone Compliant: No
License: LGPL

Description

This Core implements the Advanced Encryption Standard (Rijndael Algorithm) according to the NIST standard as documented in FIPS-197.
This AES core is developed for a key size of 128 bits and operates in ECB mode.
The project contains a synthesizable RTL along with a Test Bench set up to verify the Core with test vectors as described in the FIPS document.

General Features

Input and Key size of 128 bits.
Operation in ECB mode.
Performance adheres to FIPS-197.
Core with high speed and low latency.
RTL and TB in VHDL.

Status

Core verified in simulation and uploaded.