The VHDL Test Bench The VHDL test bench is a collection of VHDL procedures and functions which allow the user to create their own scripting instructions for test stimulus. The stimulus script or test case contains the instructions in a regular ASCII text file. The function of the instructions is coded in VHDL as part of the test bench. The test bench VHDL package contains procedures to read, parse and execute the test script (stimulus file, test case, script). The script is evaluated in two passes. The first pass reads the instructions from the stimulus file, checks the validity of the instructions, adds valid instructions to instruction sequence (inst_sequ) and creates the variable list (defined_vars). The first pass leaves everything needed in memory and happens at time zero of the simulation. The second pass is the execution pass. Instructions are referenced by their line numbers and return the instruction text, up to 6 parameters in integer form and one text string pointer. A generation tool allows the initial test bench files to be generated from the VHDL entity definition.
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