LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Personal page of Ken Boyette

    Usernamekboyette
    FullnameKen Boyette
    Emailkboyette@c...
    Account created   28-Aug-2006 21:42:58
    Last logged in18-Oct-2006 23:05:24

    Projects

  • 1-bit Microprocessor
    This project, in VHDL, implements a single-bit microprocessor based on the now obsolete Motorola MC14500B Industrial Control Unit. The ICU is basically a logic sequencer with a 4-bit instruction unit (16-instructions). In addition to the ICU, the project has a 12-bit program counter module, jump/branch units and 16-bits of I/O.
  • 8b10b Encoder/Decoder
    This project, written in generic synthesizable VHDL, provides two separate cores for encoding and decoding byte data according to the 8b/10b protocol. 8b/10b is widely used in high speed serial communication standards that need a run-length limited, DC balanced data stream for reliable data transmission and clock recovery. The encoder accepts a parallel 8-bit raw input and generates a parallel 10-bit encoded value based on the data along with a running disparity value. The decoder does the inverse, providing a decoded 8-bit value from the 10-bit encoded input. These cores can be easily incorporated into serializer/deserializer (serdes) communications applications.
  • News

  • 8b10b_encdec Project is Posted
  •  
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.