SystemC/Verilog MD5 A MD5 hash algorithm implementation in SystemC, including the equivalent synthesizable Verilog translation
SystemC/Verilog Random Number Generator A 32 bits random number generator based on the combination of a LFSR and a CASR, that gives very good statisticall properties
128/192 AES A 128 bits and a 192 bits key length AES coprocessor focusing on very low area applications.
The 128 bit implementation takes about 500 cycles to encrypt/decrypt a block.
The 192 bit implementation takes about 280 cycles to encrypt/decrypt a block.
They were designed for very low area applications like smartcards.
SystemC/Verilog DES An area improved DES coprocessor and his equivalent Verilog description.
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