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Personal page of Victor Lopez Lorenzo
| Username | galland |
| Fullname | Victor Lopez Lorenzo |
| Email | victor.lopez@o... |
| City | Madrid |
| Country | ES |
| Account created | 02-Jan-2005 12:01:03 |
| Last logged in | 29-Nov-2008 05:09:37 |
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Skils
EMAIL: victor.lopez ([(at)]) ONO (dot) COM
Projects
sp_ram to 3p_ram WISHBONE Wrapper
This is a wrapper for an inferred single port RAM, that converts it into a Three-port RAM with one WISHBONE slave interface for each port.
Wait states are reduced to the very minimum. It provides a way to lock access to only one port at a time, and priority switching avoids deadlocks.
Very useful as a drop-in module to create configuration registers for any core.
IMA ADPCM Sound Encoder
This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device.
The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file. Compression ratio is fixed for IMA-ADPCM, being 4:1.
I2C Controller Wishbone Wrapper
This is a wrapper for the I2C controller core which transparently converts a WISHBONE transaction into an I2C operation.That is: a WB read/write of the WB address 09h of this core would schedule and execute the (long) list of commands needed to make an I2C read/write of reg 09h of an I2C device connected to the I2C controller core in OpenCores, and return the result transparently into the WB bus.
ZBT SRAM Controller
This is a ZBT SRAM controller which is Wishbone rev B.3 compatible (classic + burst r/w operations). It has been simulated and verified on a Xilinx Virtex-5 FPGA board of type ML-506. It is fully functional, but any bug reports are very welcome.
JPEG Hardware Compressor
This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288).
Image resolution is not limited. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image. Its quality is comparable to software solutions.
News
New ZBT SRAM Controller (WISHBONE compatible) released!
JPEG Hardware Compressor Core released!
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