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Personal page of Dragos Constantin Doncean
| Username | dragos_doncean |
| Fullname | Dragos Constantin Doncean |
| Email | doncean@a... |
| City | Iasi |
| State | Romania |
| Country | Romania |
| Account created | 08-Jan-2007 20:27:04 |
| Last logged in | 13-Feb-2007 19:53:52 |
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Skils
Design verification engineer, working for ASICArt Iasi, Romania.
Skills:
- Vera
- SystemC
- SystemVerilog
- Perl
- Verilog
Projects
ALU with selectable inputs and outputs
A didactical project in Verilog. It's about a core containing an ALU with selectable inputs and outputs. The design itself will be suited for Verilog beginners willing to make the next step by building a circuit having practical requirements and that is a little more complex than the ones presented in Verilog books. In the end, the users will have tested all the operator types and operator symbols existing in Verilog and will have closely observed the way Verilog performs operations with the provided operands.
The source code will also contain tests, ranging from direct tests and random tests to improved tests. I will present the advantages and disadvantages of each one of them. Improved tests will be a very good introduction to design verification concepts like BFMs, monitors, collectors and checkers. These verification environment components will be written in/adapted to Verilog, since a design verification language (DVL) like Vera is not widely used in technical universities or even more, not at home.
News
ALU with selectable inputs and outputs
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