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Personal page of Andrew Mulcock
| Username | amulcock |
| Fullname | Andrew Mulcock |
| Email | opencores@m... |
| City | cambridge |
| Country | GB |
| Account created | 22-Nov-2007 20:52:29 |
| Last logged in | 02-Dec-2008 19:33:18 |
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Projects
I/Q Constellation diagram on VGA
Do you have I/Q digital waveforms in your system ?Do you want to have a quick look at them as a constellation but don't have access to a big lump of equipment ? This block takes in a stream of I/Q pairs, and outputs them in a VGA timing format, to drive a standard VGA computer monitor. Use it for Digital TV, Digital radio, Handsets, WI-FI et all.
wishbone out port from b3 spec
Rather cheeky this, but do you like me need a simple wishbone compliant thing to check your wishbone interface against.Well in the wishbone specification Appendix A, we have a bunch of such bits defined in VHDL. So thought I'd put them into CVS, where I think they should be as a group of bits of use to every one.
srl_fifo
a collection of fifo's , made out of srl's as found in Xilinx FPGA's.Small in depth, and synchronous only, but uses small amounts of an FPGA.
Wishbone BFM
VHDL reads a file of instructions to perform Wishbone access, as if it's a wishbone master.Used in testing a Wishbone peripheral with out having to instantiate and program a 'CPU' function.
wishbone_checker
Sits on a wishbone bus, and 'monitors' what the bus does.VHDL report statements used if 'errors' or 'warnings' happen on the bus, VHDL signals used as outputs, to indicate bus faults, Prime use in simulation, but can be used on a real bus,
BigCounter
Uses the shift register technology to create a big counter, that gives out a pulse at the period specified as a generic.
Command interprator and assembler
Ever wanted to 'talk' to a WishBone or OPL bus from a keyboard ?You know , you just want to try a new core out, but don't want to instantiate a processor, and program it up in C, just to be able to write and read from a few registers. Well this is for you. It understands read and write commands, from a serial link and allows you to read and write on the bus as a bus master. Example command
To write to address 12345678 the value abab
W 12345678 abab And to read from same address, receive on next line the answer. R 12345678
> abab
baud generator
block to produce from a given clock frequency a baud rate clock and a x times baud rate enable pulse.Takes in a clock and an active high reset. Two outputs, both one clock wide active high. One at baud rate, one at x times baud rate. Parameters :
frequency of the clock in : type real in MHz: e.g. 200.0
baud rate required : type integer : e.g. 115200
Overs sample rate x : type integer : e.g. 16
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