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News
Recently finished cores - awaiting FPGA testing
posted by Miha Lampret
source: OpenCores
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20-Oct-2001
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Several cores are almost finished. Meaning RTL and test bench coding is finished, simulation of RTL and gate-level with test benches works, documentation is (or almost is) finished. We hope that as many companies and individuals as possible can take one or more of listed cores and try them in practice.
Some of the cores are listed here: Ethernet 10/100, UART16550, IDE (ATA-3/ATA-5), I2C, SDRAM/CS Memory Controller, USB 2.0 Function, VGA/LCD.
To get more information about each core, please refer to each core's specification document. They are available from core's web page. To get more information or to send us testing feedback, please use each core's mailing list.
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Copyright (c) 1999
OPENCORES.ORG. All rights reserved.
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