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OpenCores and general hardware news
Archive contains 99 news of selected type.
USB 1.1 Function IP Core Released
posted by Rudolf Usselmann
source: OpenCores/ASICS.ws
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19-Sep-2002
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Today ASICS.ws released it's USB 1.1 IP core. This is the 4th IP core from ASICS.ws in the last 4 days ! Based on the USB 2.0 IP Core, this version gets rid of the requirement for a micro-controller/CPU and performs all USB enumeration in hardware. For more information please visit: http://www.opencores.org/projects/usb1_funct/
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OpenCores releases WISHBONE Rev.B3 specifications
posted by Richard Herveille
source: OpenCores
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07-Sep-2002
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OpenCores anounced today the release of the WISHBONE System-on-Chip Interconnect Architecture Rev.B3 specifications. Go to the WISHBONE pages to download a copy.
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Musketeer Microcontroller IP Delivery System
posted by Jerry D. Harthcock
source: QuickCores
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30-Aug-2002
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Microcontroller IP Delivery System on 28-pin, .600" postage stamp features Actel ProASIC+ re-programmable FPGA, built-in programming voltages and LDOs, built-in JTAG boundary scan controller, JTAG real-time debugger, device programmer, RS-232, DAC/ADC. http://www.quickcores.com
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OpenCores Coding Guidelines
posted by Damjan Lampret
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16-Aug-2002
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Updated version of OpenCores Coding Guidelines (PDF, 271KB) is available. All new designs should follow these guidelines in order to improve IP reuse and ease integration of different OpenCores IPs.
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