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OpenCores and general hardware news
Archive contains 95 news of selected type.
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OpenSoc releases Open Source SystemC to Verilog translator
posted by Javier Castillo Villar
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04-Oct-2004
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OpenSoc Design has released its SystemC to Verilog Synthesizable Subset translator under a GPL license. To download it please visit OpenSoc
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SystemC CORDIC
posted by Winnie Cheng
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01-Oct-2004
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A SystemC CORDIC implementation has been released. Please refer to the project page for more details.
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FPGA Prototyping Board under GPL
posted by Martin Schoeberl
source: http://www.opencores.org/projects.cgi/web/acxbrd/overview
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13-Sep-2004
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JOP.design releases the jopcore module under GPL. The board is designed for soft-core development with an ACEX 1K50, RAM and Flash. The board has already been used in several projects with JOP as processor. All design files are in the format that can be used with the free version of the Eagle Layout Editor.
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