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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Jun 30 19:06:20 CEST 2008
Subject: [cvs-checkins] MODIFIED: cryptosorter ...
Date: 00/08/06 30:19:06 Added: cryptosorter/lib/bsv/BRAMFeeder/src BRAMFeeder.bsv
BRAMInitiator.bsv BRAMInitiator.v
BRAMInitiatorWires.bsv mkBRAMFeeder.sched
Log:
Adding library codes
Revision Changes Path
1.1 cryptosorter/lib/bsv/BRAMFeeder/src/BRAMFeeder.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/lib/bsv/BRAMFeeder/src/BRAMFeeder.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMFeeder.bsv
===================================================================
/*
Copyright (c) 2007 MIT
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
Author: Michael Pellauer, Nirav Dave
*/
import BRAM::*;
import BRAMInitiatorWires::*;
import GetPut::*;
import FIFO::*;
import FIFOF::*;
//import Types::*;
//import Interfaces::*;
import Debug::*;
import BRAMInitiator::*;
//A message to the PPC
typedef Bit#(32) PPCMessage;
typedef enum{
FI_Initialize,
FI_InIdle,
FI_InStartCheckRead,
FI_InStartRead,
FI_InStartTake,
FI_OutStartCheckWrite,
FI_OutStartWrite,
FI_OutStartPush,
FI_CheckLoadStore,
FI_Load,
FI_LoadTake,
FI_Store,
FI_StorePush,
FI_command
} FeederState deriving(Eq,Bits);
interface Feeder;
interface Put#(PPCMessage) ppcMessageInput;
interface Get#(PPCMessage) ppcMessageOutput;
interface BRAMInitiatorWires#(Bit#(14)) bramInitiatorWires;
endinterface
Bool feederDebug = False;
(* synthesize *)
module mkBRAMFeeder(Feeder);
// Data is held in 2 addr blocks. as
// Addr n : 1---------22222 <- 1 valid bit (otherwise all zero)
// 2 top bits of payload
// n+1 : 333333333333333 <- 3 rest of payload
//State
BRAMInitiator#(Bit#(14)) bramInit <- mkBRAMInitiator;
let bram = bramInit.bram;
//BRAM#(Bit#(16), Bit#(32)) bram <- mkBRAM_Full();
FIFOF#(PPCMessage) ppcMesgQ <- mkFIFOF();
FIFOF#(PPCMessage) ppcInstQ <- mkFIFOF();
let minReadPtr = 0;
let maxReadPtr = 31;
let minWritePtr = 32;
let maxWritePtr = 63;
let ready = True;
let debugF = debug(feederDebug);
Reg#(Bit#(14)) readPtr <- mkReg(minReadPtr);
Reg#(Bit#(14)) writePtr <- mkReg(minWritePtr);
Reg#(FeederState) state <- mkReg(FI_InStartCheckRead);
Reg#(Bit#(32)) partialRead <- mkReg(0);
Reg#(Bit#(30)) heartbeat <- mkReg(0);
//Every so often send a message to the PPC indicating we're still alive
rule beat (True);
let newheart = heartbeat + 1;
heartbeat <= newheart;
if (newheart == 0)
ppcMesgQ.enq(0);
endrule
///////////////////////////////////////////////////////////
//Initialize
///////////////////////////////////////////////////////////
//Reg#(Maybe#(Bit#(14))) initReg <- mkReg(Just(0));
//Bool ready = !isJust(initReg);
//rule initBRAM(initReg matches tagged Just .i);
// $display("Init");
// bram.write(i, 0);
// initReg <= (i == maxWritePtr) ? Nothing : Just (i + 1);
//endrule
///////////////////////////////////////////////////////////
// In goes to FPGA, Out goes back to PPC
///////////////////////////////////////////////////////////
let state_tryread = (ppcInstQ.notFull ? FI_InStartCheckRead: FI_InIdle);
let state_trywrite = (ppcMesgQ.notEmpty) ? FI_OutStartCheckWrite : FI_InIdle;
rule inStartIdle(ready && state == FI_InIdle);
if(state_tryread == FI_InIdle)
begin
state <= state_trywrite;
end
else
begin
state <= state_tryread;
end
endrule
rule inStartCheckRead(ready && state == FI_InStartCheckRead);
debugF($display("BRAM: StartCheckRead"));
bram.read_req(readPtr);
state <= FI_InStartRead;
endrule
rule inStartRead(ready && state == FI_InStartRead);
let v <- bram.read_resp();
Bool valid = (v[31] == 1);
state <= (valid) ? FI_InStartTake : state_trywrite;
debugF($display("BRAM: StartRead %h", v));
if (valid)
begin
//$display("BRAM: read fstinst [%d] = %h",readPtr, v);
partialRead <= v;
bram.read_req(readPtr+1); //
end
endrule
rule inStartTake(ready && state == FI_InStartTake);
debugF($display("BRAM: StartTake"));
let val <- bram.read_resp();
Bit#(63) pack_i = truncate({partialRead,val});
PPCMessage i = unpack(truncate(pack_i));//truncate({partialRead,val}));
ppcInstQ.enq(i);
// $display("BRAM: read sndinst [%d] = %h",readPtr+1, val);
// $display("BRAM: got PPCMessage %h",pack_i);
// $display("Getting Inst: %h %h => %h",partialRead, val, {partialRead,val});
bram.write(readPtr, 0);
readPtr <= (readPtr + 2 > maxReadPtr) ? minReadPtr : (readPtr + 2);
state <= state_trywrite;
endrule
rule inStartCheckWrite(ready && state == FI_OutStartCheckWrite);
debugF($display("BRAM: StartCheckWrite"));
bram.read_req(writePtr);
state <= FI_OutStartWrite;
endrule
rule inStartWrite(ready && state == FI_OutStartWrite);
debugF($display("BRAM: StartWrite"));
let v <- bram.read_resp();
Bool valid = (v[31] == 0);
state <= (valid) ? FI_OutStartPush : state_tryread;
if (valid) begin
$display("BRAM: write [%d] = %h",writePtr+1, ppcMesgQ.first);
bram.write(writePtr+1, ppcMesgQ.first());
ppcMesgQ.deq();
end
endrule
rule inStartPush(ready && state == FI_OutStartPush);
debugF($display("BRAM: StartPush"));
$display("BRAM: write [%d] = %h",writePtr, 32'hFFFFFFFF);
bram.write(writePtr, 32'hFFFFFFFF);//all 1s
writePtr <= (writePtr + 2 > maxWritePtr) ? minWritePtr : (writePtr + 2);
state <= state_tryread;
endrule
//Interface
interface ppcMessageInput = fifoToPut(fifofToFifo(ppcMesgQ));
interface ppcMessageOutput = fifoToGet(fifofToFifo(ppcInstQ));
interface bramInitiatorWires = bramInit.bramInitiatorWires;
endmodule
1.1 cryptosorter/lib/bsv/BRAMFeeder/src/BRAMInitiator.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/lib/bsv/BRAMFeeder/src/BRAMInitiator.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMInitiator.bsv
===================================================================
/*
Copyright (c) 2007 MIT
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
Author: Kermin Fleming
*/
import BRAMInitiatorWires::*;
import BRAM::*;
interface BRAMInitiator#(type idx_type);
interface BRAM#(idx_type, Bit#(32)) bram;
interface BRAMInitiatorWires#(idx_type) bramInitiatorWires;
endinterface
interface BRAMInitiatorFlat#(type idx_type);
method ActionValue#(Bit#(32)) read_resp();
method Action read_req(idx_type idx);
method Action write(idx_type idx, Bit#(32) value);
method Bit#(1) bramCLK();
method Bit#(1) bramRST();
method idx_type bramAddr();
method Bit#(32) bramDout();
method Action bramDin(Bit#(32) value);
method Bit#(4) bramWEN();
method Bit#(1) bramEN();
endinterface
module mkBRAMInitiator (BRAMInitiator#(idx_type))
provisos
(Bits#(idx_type, idx),
Literal#(idx_type));
BRAMInitiatorFlat#(idx_type) bramFlat <- mkBRAMInitiatorFlat();
interface BRAM bram;
method write = bramFlat.write;
method read_req = bramFlat.read_req;
method read_resp = bramFlat.read_resp;
endinterface
interface BRAMInitiatorWires bramInitiatorWires;
method bramCLK = bramFlat.bramCLK;
method bramRST = bramFlat.bramRST;
method bramAddr = bramFlat.bramAddr;
method bramDout = bramFlat.bramDout;
method bramDin = bramFlat.bramDin;
method bramWEN = bramFlat.bramWEN;
method bramEN = bramFlat.bramEN;
endinterface
endmodule
import "BVI" BRAMInitiator = module mkBRAMInitiatorFlat
//interface:
(BRAMInitiatorFlat#(idx_type))
provisos
(Bits#(idx_type, idx),
Literal#(idx_type));
default_clock clk(CLK);
parameter addr_width = valueof(idx);
method DOUT read_resp() ready(DOUT_RDY) enable(DOUT_EN);
method read_req(RD_ADDR) ready(RD_RDY) enable(RD_EN);
method write(WR_ADDR, WR_VAL) enable(WR_EN);
method BRAM_CLK bramCLK();
method BRAM_RST bramRST();
method BRAM_Addr bramAddr();
method BRAM_Dout bramDout();
method bramDin(BRAM_Din) enable(BRAM_Dummy_Enable);
method BRAM_WEN bramWEN();
method BRAM_EN bramEN();
schedule read_req CF (read_resp, write, bramCLK, bramRST, bramAddr, bramDout, bramDin, bramWEN, bramEN);
schedule read_resp CF (read_req, write, bramCLK, bramRST, bramAddr, bramDout, bramDin, bramWEN, bramEN);
schedule write CF (read_req, read_resp, bramCLK, bramRST, bramAddr, bramDout, bramDin, bramWEN, bramEN);
// All the BRAM methods are CF
schedule bramCLK CF (read_resp, read_req, write, bramCLK, bramRST, bramAddr, bramDout, bramDin, bramWEN, bramEN);
schedule bramRST CF (read_resp, read_req, write, bramCLK, bramRST, bramAddr, bramDout, bramDin, bramWEN, bramEN);
schedule bramAddr CF (read_resp, read_req, write, bramCLK, bramRST, bramAddr, bramDout, bramDin, bramWEN, bramEN);
schedule bramDout CF (read_resp, read_req, write, bramCLK, bramRST, bramAddr, bramDout, bramDin, bramWEN, bramEN);
schedule bramDin CF (read_resp, read_req, write, bramCLK, bramRST, bramAddr, bramDout, bramDin, bramWEN, bramEN);
schedule bramWEN CF (read_resp, read_req, write, bramCLK, bramRST, bramAddr, bramDout, bramDin, bramWEN, bramEN);
schedule bramEN CF (read_resp, read_req, write, bramCLK, bramRST, bramAddr, bramDout, bramDin, bramWEN, bramEN);
schedule read_req C read_req;
schedule read_resp C read_resp;
schedule write C write;
endmodule
1.1 cryptosorter/lib/bsv/BRAMFeeder/src/BRAMInitiator.v
http://www.opencores.org/cvsweb.shtml/cryptosorter/lib/bsv/BRAMFeeder/src/BRAMInitiator.v?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMInitiator.v
===================================================================
/*
Copyright (c) 2007 MIT
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
Author: Kermin Fleming
*/
module BRAMInitiator(CLK, RST_N,
RD_ADDR, RD_RDY, RD_EN,
DOUT, DOUT_RDY, DOUT_EN,
WR_ADDR, WR_VAL, WR_EN,
BRAM_Addr, BRAM_Dout, BRAM_Din,BRAM_Dummy_Enable,
BRAM_WEN, BRAM_EN, BRAM_RST,
BRAM_CLK);
// synopsys template
parameter addr_width = 1;
input CLK;
input RST_N;
// Read Port
// req
input [addr_width -1 : 0] RD_ADDR;
input RD_EN;
output RD_RDY;
// resp
output [31 : 0] DOUT;
output DOUT_RDY;
input DOUT_EN;
// Write Port
// req
input [addr_width - 1 : 0] WR_ADDR;
input [31 : 0] WR_VAL;
input WR_EN;
// BRAM Wires
output [addr_width - 1 : 0] BRAM_Addr;
output [31 : 0] BRAM_Dout;
input [31 : 0] BRAM_Din;
input BRAM_Dummy_Enable;
output [3 : 0] BRAM_WEN;
output BRAM_EN;
output BRAM_RST;
output BRAM_CLK;
// Assignments
assign BRAM_CLK = CLK;
assign BRAM_EN = RST_N; // disable the BRAM if we are in reset
assign BRAM_RST = 1'b0; // Never reset the BRAM.
assign BRAM_Addr = (WR_EN)?(WR_ADDR):(RD_ADDR);
assign BRAM_WEN = {WR_EN,WR_EN,WR_EN,WR_EN};
assign BRAM_Dout = WR_VAL;
reg RD_REQ_MADE;
reg [1:0] CTR;
/*always@(BRAM_Din)
$display("BRAMInitiator.v BRAM_Din: %x",BRAM_Din);
*/
FIFO2#(.width(32)) q(.RST_N(RST_N),
.CLK(CLK),
.D_IN(BRAM_Din),
.ENQ(RD_REQ_MADE),
.DEQ(DOUT_EN),
.CLR(1'b0),
.D_OUT(DOUT),
.FULL_N(),
.EMPTY_N(DOUT_RDY));
assign RD_RDY = (CTR > 0);
always@(posedge CLK)
begin
if (!RST_N)
begin
CTR <= 2;
end
else
begin
/*if(RD_EN)
$display("BRAMInitiator: RD_EN");
if(WR_EN)
$display("BRAMInitiator: WR_EN");
*/
RD_REQ_MADE <= RD_EN;
CTR <= (RD_EN) ?
(DOUT_EN) ? CTR : CTR - 1 :
(DOUT_EN) ? CTR + 1 : CTR;
end
end // always@ (posedge CLK)
endmodule
1.1 cryptosorter/lib/bsv/BRAMFeeder/src/BRAMInitiatorWires.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/lib/bsv/BRAMFeeder/src/BRAMInitiatorWires.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMInitiatorWires.bsv
===================================================================
/*
Copyright (c) 2007 MIT
Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
Author: Kermin Fleming
*/
interface BRAMInitiatorWires#(type idx_type);
(* always_ready, always_enabled, prefix="" *)
method Bit#(1) bramCLK();
(* always_ready, always_enabled, prefix="" *)
method Bit#(1) bramRST();
(* always_ready, always_enabled, prefix="" *)
method idx_type bramAddr();
(* always_ready, always_enabled, prefix="" *)
method Bit#(32) bramDout();
(* always_ready, always_enabled, prefix="" *)
method Action bramDin(Bit#(32) din);
(* always_ready, always_enabled, prefix="" *)
method Bit#(4) bramWEN();
(* always_ready, always_enabled, prefix="" *)
method Bit#(1) bramEN();
endinterface
1.1 cryptosorter/lib/bsv/BRAMFeeder/src/mkBRAMFeeder.sched
http://www.opencores.org/cvsweb.shtml/cryptosorter/lib/bsv/BRAMFeeder/src/mkBRAMFeeder.sched?rev=1.1&content-type=text/x-cvsweb-markup
Index: mkBRAMFeeder.sched
===================================================================
=== Generated schedule for mkBRAMFeeder ===
Method schedule
---------------
Method: ppcMessageInput_put
Ready signal: ppcMesgQ.i_notFull && ppcMesgQ.notFull
Conflict-free: bramInitiatorWires_bramCLK,
bramInitiatorWires_bramRST,
bramInitiatorWires_bramAddr,
bramInitiatorWires_bramDout,
bramInitiatorWires_bramDin,
bramInitiatorWires_bramWEN,
bramInitiatorWires_bramEN
Sequenced before (restricted): ppcMessageOutput_get
Conflicts: ppcMessageInput_put
Method: ppcMessageOutput_get
Ready signal: ppcInstQ.notEmpty && ppcInstQ.i_notEmpty
Conflict-free: bramInitiatorWires_bramCLK,
bramInitiatorWires_bramRST,
bramInitiatorWires_bramAddr,
bramInitiatorWires_bramDout,
bramInitiatorWires_bramDin,
bramInitiatorWires_bramWEN,
bramInitiatorWires_bramEN
Sequenced after (restricted): ppcMessageInput_put
Conflicts: ppcMessageOutput_get
Method: bramInitiatorWires_bramCLK
Ready signal: True
Conflict-free: ppcMessageInput_put,
ppcMessageOutput_get,
bramInitiatorWires_bramCLK,
bramInitiatorWires_bramRST,
bramInitiatorWires_bramAddr,
bramInitiatorWires_bramDout,
bramInitiatorWires_bramDin,
bramInitiatorWires_bramWEN,
bramInitiatorWires_bramEN
Method: bramInitiatorWires_bramRST
Ready signal: True
Conflict-free: ppcMessageInput_put,
ppcMessageOutput_get,
bramInitiatorWires_bramCLK,
bramInitiatorWires_bramRST,
bramInitiatorWires_bramAddr,
bramInitiatorWires_bramDout,
bramInitiatorWires_bramDin,
bramInitiatorWires_bramWEN,
bramInitiatorWires_bramEN
Method: bramInitiatorWires_bramAddr
Ready signal: True
Conflict-free: ppcMessageInput_put,
ppcMessageOutput_get,
bramInitiatorWires_bramCLK,
bramInitiatorWires_bramRST,
bramInitiatorWires_bramAddr,
bramInitiatorWires_bramDout,
bramInitiatorWires_bramDin,
bramInitiatorWires_bramWEN,
bramInitiatorWires_bramEN
Method: bramInitiatorWires_bramDout
Ready signal: True
Conflict-free: ppcMessageInput_put,
ppcMessageOutput_get,
bramInitiatorWires_bramCLK,
bramInitiatorWires_bramRST,
bramInitiatorWires_bramAddr,
bramInitiatorWires_bramDout,
bramInitiatorWires_bramDin,
bramInitiatorWires_bramWEN,
bramInitiatorWires_bramEN
Method: bramInitiatorWires_bramDin
Ready signal: True
Conflict-free: ppcMessageInput_put,
ppcMessageOutput_get,
bramInitiatorWires_bramCLK,
bramInitiatorWires_bramRST,
bramInitiatorWires_bramAddr,
bramInitiatorWires_bramDout,
bramInitiatorWires_bramDin,
bramInitiatorWires_bramWEN,
bramInitiatorWires_bramEN
Method: bramInitiatorWires_bramWEN
Ready signal: True
Conflict-free: ppcMessageInput_put,
ppcMessageOutput_get,
bramInitiatorWires_bramCLK,
bramInitiatorWires_bramRST,
bramInitiatorWires_bramAddr,
bramInitiatorWires_bramDout,
bramInitiatorWires_bramDin,
bramInitiatorWires_bramWEN,
bramInitiatorWires_bramEN
Method: bramInitiatorWires_bramEN
Ready signal: True
Conflict-free: ppcMessageInput_put,
ppcMessageOutput_get,
bramInitiatorWires_bramCLK,
bramInitiatorWires_bramRST,
bramInitiatorWires_bramAddr,
bramInitiatorWires_bramDout,
bramInitiatorWires_bramDin,
bramInitiatorWires_bramWEN,
bramInitiatorWires_bramEN
Rule schedule
-------------
Rule: inStartPush
Predicate: state == 4'd7
Blocking rules: (none)
Rule: inStartWrite
Predicate: bramInit_bramFlat.RDY_read_resp && ppcMesgQ.i_notEmpty &&
(state == 4'd6)
Blocking rules: ppcMessageInput_put
Rule: inStartCheckWrite
Predicate: bramInit_bramFlat.RDY_read_req && (state == 4'd5)
Blocking rules: (none)
Rule: inStartTake
Predicate: bramInit_bramFlat.RDY_read_resp && ppcInstQ.i_notFull &&
(state == 4'd4)
Blocking rules: ppcMessageInput_put
Rule: inStartRead
Predicate: bramInit_bramFlat.RDY_read_resp &&
bramInit_bramFlat.RDY_read_req &&
(state == 4'd3)
Blocking rules: (none)
Rule: inStartCheckRead
Predicate: bramInit_bramFlat.RDY_read_req && (state == 4'd2)
Blocking rules: (none)
Rule: inStartIdle
Predicate: state == 4'd1
Blocking rules: (none)
Rule: beat
Predicate: (! (heartbeat == 30'd1073741823)) || ppcMesgQ.i_notFull
Blocking rules: ppcMessageInput_put
Logical execution order: bramInitiatorWires_bramEN,
bramInitiatorWires_bramWEN,
bramInitiatorWires_bramDin,
bramInitiatorWires_bramDout,
bramInitiatorWires_bramAddr,
bramInitiatorWires_bramRST,
bramInitiatorWires_bramCLK,
inStartRead,
inStartIdle,
ppcMessageInput_put,
inStartPush,
inStartWrite,
ppcMessageOutput_get,
inStartCheckWrite,
inStartTake,
inStartCheckRead,
beat
============================================
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