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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Jun 30 19:06:18 CEST 2008
Subject: [cvs-checkins] MODIFIED: cryptosorter ...
Date: 00/08/06 30:19:06 Added: cryptosorter/lib/bsv/BRAMFIFO BRAMFIFO.bsv BRAMFIFOF.v
mkTestBench.bsv readme.txt top.v
Log:
Adding library codes
Revision Changes Path
1.1 cryptosorter/lib/bsv/BRAMFIFO/BRAMFIFO.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/lib/bsv/BRAMFIFO/BRAMFIFO.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMFIFO.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Kermin Fleming, kfleming@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
import FIFO::*;
import FIFOF::*;
import FIFOF_::*;
/***
*
* This module serves as a simple bluespec wrapper for
* the verilog based BRAMFIFO. The imported methods support
* the standard FIFOF and FIFO classes. It should be noted that
* the underlying verilog implementation is gaurded.
*
***/
module mkBRAMFIFO#(Integer count) (FIFO#(fifo_type))
provisos
(Bits#(fifo_type, fifo_size));
FIFOF#(fifo_type) fifo <- mkBRAMFIFOF(count);
method Action enq(fifo_type data);
fifo.enq(data);
endmethod
method Action deq();
fifo.deq();
endmethod
method fifo_type first();
return fifo.first();
endmethod
method Action clear();
fifo.clear();
endmethod
endmodule
module mkBRAMFIFOF#(Integer count) (FIFOF#(fifo_type))
provisos
(Bits#(fifo_type, fifo_size));
FIFOF_#(fifo_type) fifo <- mkBRAMFIFOF_(count);
method Action enq(fifo_type data) if(fifo.i_notFull);
fifo.enq(data);
endmethod
method Action deq() if(fifo.i_notEmpty);
fifo.deq();
endmethod
method fifo_type first() if(fifo.i_notEmpty);
return fifo.first();
endmethod
method Bool notFull;
return fifo.notFull;
endmethod
method Bool notEmpty;
return fifo.notEmpty;
endmethod
method Action clear();
fifo.clear();
endmethod
endmodule
import "BVI" BRAMFIFOF = module mkBRAMFIFOF_#(Integer count)
//interface:
(FIFOF_#(fifo_type))
provisos
(Bits#(fifo_type, fifo_size));
default_clock clk(CLK);
parameter log_data_count = log2(count);
parameter data_count = count;
parameter data_width = valueOf(fifo_size);
method enq((* reg *)D_IN) enable(ENQ);
method deq() enable(DEQ);
method (* reg *)D_OUT first;
method FULL_N notFull;
method FULL_N i_notFull;
method (* reg *)EMPTY_N notEmpty;
method (* reg *)EMPTY_N i_notEmpty;
method clear() enable(CLR);
schedule deq CF (enq, i_notEmpty, i_notFull) ;
schedule enq CF (deq, first, i_notEmpty, i_notFull) ;
schedule (first, notEmpty, notFull) CF
(first, i_notEmpty, i_notFull, notEmpty, notFull) ;
schedule (i_notEmpty, i_notFull) CF
(clear, first, i_notEmpty, i_notFull, notEmpty, notFull) ;
schedule (clear, deq, enq) SBR clear ;
schedule first SB (clear, deq) ;
schedule (notEmpty, notFull) SB (clear, deq, enq) ;
/*schedule first SB (deq,enq,clear);
schedule first CF (first,notFull,notEmpty);
schedule notFull SB (deq,enq,clear);
schedule notFull CF (first,notFull,notEmpty);
schedule notEmpty SB (deq,enq,clear);
schedule notEmpty CF (first,notFull,notEmpty);
schedule deq CF enq;
schedule deq SB clear;
schedule deq C deq;
schedule enq CF deq;
schedule enq SB clear;
schedule enq C enq;
schedule clear C clear;*/
endmodule
1.1 cryptosorter/lib/bsv/BRAMFIFO/BRAMFIFOF.v
http://www.opencores.org/cvsweb.shtml/cryptosorter/lib/bsv/BRAMFIFO/BRAMFIFOF.v?rev=1.1&content-type=text/x-cvsweb-markup
Index: BRAMFIFOF.v
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Kermin Fleming, kfleming@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
/***
*
* This module implements a parametric verilog sized fifo. This particular
* sized fifo will synthesize on to Xilinx block rams. The fifo is parametric
* in terms of both data width and the number of data stored in the fifo.
* the interface is gaurded. The fifo is not loopy.
* The methods supported by the FIFO are clear, dequeue, enqueue, notFull,
* and notEmpty
*
***/
module BRAMFIFOF(CLK, RST_N,
D_IN, CLR, DEQ,
ENQ, D_OUT, FULL_N, EMPTY_N);
// synopsys template
parameter log_data_count = 0;
parameter data_count = 1;
parameter data_width = 1;
input CLK;
input RST_N;
input [data_width - 1 : 0] D_IN;
input CLR;
input DEQ;
input ENQ;
output [data_width - 1 : 0] D_OUT;
output FULL_N;
output EMPTY_N;
reg [data_width - 1 : 0] arr[0:data_count]; /*synthesis syn_ramstyle = "block_ram"*/
reg skid_flag;
reg [log_data_count + 2 : 0] fifo_data_count;
reg [log_data_count + 2 : 0] read_ptr;
reg [log_data_count + 2 : 0] read_ptr_current;
reg [log_data_count + 2 : 0] write_ptr;
reg [data_width - 1 : 0] skid_buffer; // this is a fast output buffer
reg [data_width - 1 : 0] RAM_OUT;
assign D_OUT = (skid_flag)?skid_buffer:RAM_OUT;
assign FULL_N = !(fifo_data_count == data_count);
assign EMPTY_N = !(fifo_data_count == 0);
integer x;
always@(*)
begin
if(DEQ)
begin
read_ptr_current = (read_ptr == data_count)?0:(read_ptr + 1);
end
else
begin
read_ptr_current = read_ptr;
end
end
always@(posedge CLK)
begin
if (!RST_N)
begin //Make simulation behavior consistent with Xilinx synthesis
// synopsys translate_off
for (x = 0; x < data_count + 1; x = x + 1)
begin
arr[x] <= 0;
end
// synopsys translate_on
fifo_data_count <= 0;
skid_buffer <= 0;
skid_flag <= 0;
read_ptr <= 0;
write_ptr <= 0;
//$display("Params: data_count: %d, log_data_count: %d, data_width: %d", data_count, log_data_count, data_width);
end
else
begin
// assign output buffer
skid_buffer <= D_IN;
if(CLR)
begin
skid_flag <= 0;
end
else if(ENQ && ((fifo_data_count == 0) || ((fifo_data_count == 1) && DEQ)))
begin
//$display("Enque to output buffer");
skid_flag <= 1;
end
else
begin
skid_flag <= 0;
end
// write_ptr
if(CLR)
begin
write_ptr <= 0;
end
else if(ENQ)
begin
//$display("Enque to BRAM[%d]: %d", write_ptr,D_IN);
write_ptr <= (write_ptr == data_count)?0:(write_ptr + 1);
end
else
begin
write_ptr <= write_ptr;
end
//read_ptr
if(CLR)
begin
read_ptr <= 0;
end
else if(DEQ)
begin
//$display("Advancing read ptr");
read_ptr <= (read_ptr == data_count)?0:(read_ptr + 1);
end
else
begin
read_ptr <= read_ptr;
end
// assign fifo data_count
if(CLR)
begin
fifo_data_count <= 0;
end
else if(ENQ && DEQ)
begin
fifo_data_count <= fifo_data_count;
end
else if(ENQ)
begin
fifo_data_count <= fifo_data_count + 1;
end
else if(DEQ)
begin
fifo_data_count <= fifo_data_count - 1;
end
else
begin
fifo_data_count <= fifo_data_count;
end
if(ENQ)
begin
arr[write_ptr] <= D_IN;
end
RAM_OUT <= arr[read_ptr_current];
end
end // always@ (posedge CLK)
endmodule
1.1 cryptosorter/lib/bsv/BRAMFIFO/mkTestBench.bsv
http://www.opencores.org/cvsweb.shtml/cryptosorter/lib/bsv/BRAMFIFO/mkTestBench.bsv?rev=1.1&content-type=text/x-cvsweb-markup
Index: mkTestBench.bsv
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Kermin Fleming, kfleming@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
import BRAMFIFO::*;
import FIFOF::*;
import FIFO::*;
/***
*
* This module is a test harness for the BRAMFIFO verilog module.
* The module compares the behavior of a BRAM based sized FIFO and a
* standard sized fifo. If their behavior differs at any point during the
* long pseudo-random test bench, then a failure message is displayed.
*
***/
(* synthesize *)
module mkTest (FIFOF#(Bit#(32)));
FIFOF#(Bit#(32)) gold <- mkBRAMFIFOF(250);
FIFO#(Bit#(32)) p <- mkSizedFIFO(6);
return gold;
endmodule
module mkTestBench ();
Reg#(Bit#(32)) test_counter <- mkReg(0);
rule test_counter_rl;
test_counter <= test_counter + 1;
if(test_counter > 1000000)
begin
$display("PASS");
$finish;
end
endrule
for(Integer i = 2; i < 4; i = i + 1)
begin
FIFO#(Bit#(32)) gold <- mkSizedFIFO(i);
FIFO#(Bit#(32)) test <- mkBRAMFIFO(i);
Reg#(Bit#(32)) counter <- mkReg(0);
rule count;
counter <= counter + 1;
endrule
rule enq_a(counter % fromInteger(i) == 0);
gold.enq(counter);
endrule
rule enq_b(counter % fromInteger(i) == 0);
test.enq(counter);
endrule
for(Integer j = 2; j < 4; j = j+1)
begin
rule deq_check(zeroExtend(counter)%fromInteger(j) == 0);
if(gold.first() != test.first())
begin
$display("FAIL Not equal! g: %d t: %d i: %d j: %d", gold.first, test.first, i, j);
end
else
begin
$display("Match: %d i:%d j:%d", gold.first, i,j);
end
gold.deq;
test.deq;
endrule
end
end
endmodule
1.1 cryptosorter/lib/bsv/BRAMFIFO/readme.txt
http://www.opencores.org/cvsweb.shtml/cryptosorter/lib/bsv/BRAMFIFO/readme.txt?rev=1.1&content-type=text/x-cvsweb-markup
Index: readme.txt
===================================================================
BRAM.bsv and BRAM.v are a bluespec wrapper for a synthesizable fpga BRAM. blue_sim_model directory contains a wholly bluespec cycle accurate model of the BRAM which can be used for simulation/debugging.
These files were created by
Kermin Fleming (MIT)
Micheal Pellauer (MIT)
Eric Chung (CMU)
Caveat Codor.
1.1 cryptosorter/lib/bsv/BRAMFIFO/top.v
http://www.opencores.org/cvsweb.shtml/cryptosorter/lib/bsv/BRAMFIFO/top.v?rev=1.1&content-type=text/x-cvsweb-markup
Index: top.v
===================================================================
//----------------------------------------------------------------------//
// The MIT License
//
// Copyright (c) 2008 Kermin Fleming, kfleming@m...
//
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use,
// copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//----------------------------------------------------------------------//
module top;
reg clk;
reg rst_n;
mkTestBench m(.CLK(clk),.RST_N(rst_n));
always@(clk)
#5 clk <= ~clk;
initial
begin
$dumpfile("dump.vcd");
$dumpvars(4,m);
rst_n <= 0;
clk <= 0;
#50;
rst_n <= 1;
end
endmodule
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