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From: cvs at opencores.org<cvs@o...>
Date: Mon Jun 30 18:02:14 CEST 2008
Subject: [cvs-checkins] MODIFIED: cryptosorter ...
Date: 00/08/06 30:18:02

Added: cryptosorter/memocodeDesignContest2008/xup/PLBMaster
PLBMaster.bsv PLBMasterBackup.bsv
PLBMasterDummy.bsv PLBMasterMagic.bsv
PLBMasterTester.bsv PLBMasterWires.bsv
PLBMaster_backupPPC.bsv PLBModel.bsv PLBSlave.bsv
mkPLBMaster.sched mkPLBMasterTester.sched
plbmastertester.v
Log:
Initial checkin with actual source




Revision Changes Path
1.1 cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMaster.bsv

http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMaster.bsv?rev=1.1&content-type=text/x-cvsweb-markup

Index: PLBMaster.bsv
===================================================================
/*
Copyright (c) 2007 MIT

Permission is hereby granted, free of charge, to any person
obtaining a copy of this software and associated documentation
files (the "Software"), to deal in the Software without
restriction, including without limitation the rights to use,
copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following
conditions:

The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.

Author: Kermin Fleming
*/

/* This file implements a PLB bus master. The bus master operates on static
sized bursts. It is written in such a way that read/write bursts may be
overlapped, if the bus and target slave support such a feature. There's also
support for pipelining of read and write requests. The master is
parameterized by BeatsPerBurst (burst length) and BusWord (bus width),
which allow it to be used for various applications.
*/

// Global Imports
import GetPut::*;
import FIFO::*;
import RegFile::*;
import BRAMInitiatorWires::*;
import RegFile::*;
import FIFOF::*;
import Vector::*;

import Types::*;
import Interfaces::*;
import Parameters::*;
import DebugFlags::*;

import PLBMasterWires::*;
import Memocode08Types::*;

typedef enum {
Idle,
Data,
WaitForBusy
} StateTransfer
deriving(Bits, Eq);

typedef enum {
Idle,
RequestingLoad,
RequestingStore
} StateRequest
deriving(Bits, Eq);

(* synthesize *)
module mkPLBMaster (PLBMaster);
Clock plbClock <- exposeCurrentClock();
Reset plbReset <- exposeCurrentReset();
// state for the actual magic memory hardware
FIFO#(Record) recordInfifo <- mkFIFO;
FIFO#(Record) recordOutfifo <- mkFIFO;
FIFO#(PLBMasterCommand) plbMasterCommandInfifo <- mkFIFO();


// Output buffer
RegFile#(Bit#(TAdd#(1,TLog#(BeatsPerBurst))),BusWord) storeBuffer <- mkRegFileFull();


// Input buffer RegFile#(Bit#(TAdd#(1,TLog#(BeatsPerBurst))),BusWord) loadBuffer <- mkRegFileFull(); Reg#(Bit#(24)) rowAddrOffsetLoad <- mkReg(0); Reg#(Bit#(24)) rowAddrOffsetStore <- mkReg(0); Reg#(Bool) doingLoad <- mkReg(False); Reg#(Bool) doingStore <- mkReg(False); Bit#(TLog#(TMul#(BeatsPerBurst, WordsPerBeat))) zeroOffset = 0; // Words per Burst Reg#(Bool) requestingStore <- mkReg(False); BlockAddr addressOffset = zeroExtend({(requestingStore)?rowAddrOffsetStore:rowAddrOffsetLoad,zeroOffset}); Reg#(StateRequest) stateRequest <- mkReg(Idle); Reg#(StateTransfer) stateLoad <- mkReg(Idle); Reg#(StateTransfer) stateStore <- mkReg(Idle); Reg#(Bit#(1)) request <- mkReg(0); Reg#(Bit#(1)) rnw <- mkReg(0); Reg#(Bit#(TLog#(BeatsPerBurst))) loadDataCount <- mkReg(0); Reg#(Bit#(TLog#(BeatsPerBurst))) storeDataCount <-mkReg(0);// If you change this examine mWrDBus_o Reg#(Bit#(TAdd#(1,TLog#(BeatsPerBurst)))) loadDataCount_plus2 <- mkReg(2); Reg#(Bit#(TAdd#(1,TLog#(BeatsPerBurst)))) storeDataCount_plus2 <-mkReg(2); Reg#(Bool) doAckinIdle <- mkReg(False); Reg#(Bit#(1)) rdBurst <- mkReg(0); Reg#(Bit#(1)) wrBurst <- mkReg(0); Reg#(Bit#(1)) storeCounter <- mkReg(0); Reg#(Bit#(1)) loadCounter <- mkReg(0); Reg#(Bit#(TAdd#(1,TLog#(BeatsPerBurst)))) storeBufferWritePointer <- mkReg(0); FIFOF#(Bit#(0)) storeValid <- mkUGFIFOF;//XXX: This could be bad Reg#(Bit#(TAdd#(1,TLog#(BeatsPerBurst)))) loadBufferReadPointer <- mkReg(0); FIFOF#(Bit#(0)) loadValid <- mkUGFIFOF;//XXX: This could be bad // Input wires Wire#(Bit#(1)) mRst <- mkBypassWire(); Wire#(Bit#(1)) mAddrAck <- mkBypassWire(); Wire#(Bit#(1)) mBusy <- mkBypassWire(); Wire#(Bit#(1)) mErr <- mkBypassWire(); Wire#(Bit#(1)) mRdBTerm <- mkBypassWire(); Wire#(Bit#(1)) mRdDAck <- mkBypassWire(); Wire#(Bit#(64))mRdDBus <- mkBypassWire(); Wire#(Bit#(3)) mRdWdAddr <- mkBypassWire(); Wire#(Bit#(1)) mRearbitrate <- mkBypassWire(); Wire#(Bit#(1)) mWrBTerm <- mkBypassWire(); Wire#(Bit#(1)) mWrDAck <- mkBypassWire(); Wire#(Bit#(1)) mSSize <- mkBypassWire(); Wire#(Bit#(1)) sMErr <- mkBypassWire(); // on a read, during the data ack Wire#(Bit#(1)) sMBusy <- mkBypassWire(); // Outputs Bit#(PLBAddrSize) mABus_o = {addressOffset,2'b00}; // Our address Address Bus, we extend to compensate for word Bit#(TAdd#(1,TLog#(BeatsPerBurst))) sbuf_addr = {storeCounter,storeDataCount}; Bit#(64)mWrDBus_o = storeBuffer.sub(sbuf_addr); Bit#(1) mRequest_o = request & ~mRst; // Request Bit#(1) mBusLock_o = 1'b0 & ~mRst; // Bus lock Bit#(1) mRdBurst_o = rdBurst & ~mRst; // read burst Bit#(1) mWrBurst_o = wrBurst & ~mRst; // write burst Bit#(1) mRNW_o = rnw; // Read Not Write Bit#(1) mAbort_o = 1'b0; // Abort Bit#(2) mPriority_o = 2'b11;// priority indicator Bit#(1) mCompress_o = 1'b0;// compressed transfer Bit#(1) mGuarded_o = 1'b0;// guarded transfer Bit#(1) mOrdered_o = 1'b0;// synchronize transfer Bit#(1) mLockErr_o = 1'b0;// lock erro Bit#(4) mSize_o = 4'b1011; // Burst double word transfer - see PLB p.24 Bit#(3) mType_o = 3'b000; // Memory Transfer Bit#(8) mBE_o = 8'b00001111; // 16 word burst Bit#(2) mMSize_o = 2'b00; // precompute the next address offset. Sometimes PLBMasterCommand cmd_in_first = plbMasterCommandInfifo.first(); let newloadDataCount = loadDataCount + 1; let newstoreDataCount = storeDataCount + 1; let newloadDataCount_plus2 = loadDataCount_plus2 + 1; let newstoreDataCount_plus2 = storeDataCount_plus2 + 1; rule startPageLoad(cmd_in_first matches tagged LoadPage .ba &&& !doingLoad); $display("Start Page"); plbMasterCommandInfifo.deq(); $display("Load Page"); rowAddrOffsetLoad <= truncate(ba>>(valueof(TLog#(TMul#(BeatsPerBurst, WordsPerBeat))))); // this is the log if (ba[3:0] != 0) $display("ERROR:Address not 64-byte aligned"); doingLoad <= True; endrule rule startPageStore(cmd_in_first matches tagged StorePage .ba &&& !doingStore); $display("Start Page"); plbMasterCommandInfifo.deq(); $display("Store Page"); rowAddrOffsetStore <= truncate(ba>>(valueof(TLog#(TMul#(BeatsPerBurst, WordsPerBeat))))); // this is the log // size of burst addr if (ba[3:0] != 0) $display("ERROR:Address not 64-byte aligned"); doingStore <= True; endrule rule loadPage_Idle(doingLoad && stateRequest == Idle && stateLoad == Idle); // We should not initiate a transfer if the wordOutfifo is not valid //$display("loadPage_Idle"); requestingStore <= False; if(loadValid.notFull())// Check for a spot. begin request <= 1'b1; stateRequest <= RequestingLoad; end else begin request <= 1'b0; // Not Sure this is needed end rnw <= 1'b1; // We're reading endrule rule loadPage_Requesting(doingLoad && stateRequest == RequestingLoad && stateLoad == Idle); // We've just requested the bus and are waiting for an ack //$display("loadPage_Requesting"); if(mAddrAck == 1 ) begin stateRequest <= Idle; // Check for error conditions if(mRearbitrate == 1) begin // Got terminated by the bus $display("Terminated by BUS @ %d",$time); stateLoad <= Idle; rdBurst <= 1'b0; // if we're rearbing this should be off. It may be off anyway? request <= 1'b0; end else begin //Whew! didn't die yet.. wait for acks to come back stateLoad <= Data; // Not permissible to assert burst until after addrAck p. 35 rdBurst <= 1'b1; // Set down request, as we are not request pipelining request <= 1'b0; end end endrule rule loadPage_Data(doingLoad && stateLoad == Data); if(((mRdBTerm == 1) && (loadDataCount_plus2 < (fromInteger(valueof(BeatsPerBurst))))) || (mErr == 1)) begin // We got terminated / Errored rdBurst <= 1'b0; loadDataCount <= 0; loadDataCount_plus2 <= 2; stateLoad <= Idle; end else if(mRdDAck == 1) begin loadDataCount <= newloadDataCount; loadDataCount_plus2 <= newloadDataCount_plus2; loadBuffer.upd({loadCounter,loadDataCount}, mRdDBus); if(newloadDataCount == 0) begin loadCounter <= loadCounter + 1; // Flip the loadCounter //We're now done reading... what should we do? loadValid.enq(0); // This signifies that the data is valid Nirav could probably remove this doingLoad <= False; stateLoad <= Idle; end else if(newloadDataCount == maxBound) // YYY: ndave used to ~0 begin // Last read is upcoming. Need to set down the // rdBurst signal. rdBurst <= 1'b0; end end endrule rule storePage_Idle(doingStore && stateRequest == Idle && stateStore == Idle); requestingStore <= True; if(storeValid.notEmpty()) begin request <= 1'b1; stateRequest <= RequestingStore; end else begin request <= 1'b0; end wrBurst <= 1'b1; // Write burst is asserted with the write request rnw <= 1'b0; // We're writing endrule rule storePage_Requesting(doingStore && stateRequest == RequestingStore && stateStore == Idle); // We've just requested the bus and are waiting for an ack if(mAddrAck == 1 ) begin stateRequest <= Idle; // Check for error conditions if(mRearbitrate == 1) begin // Got terminated by the bus wrBurst <= 1'b0; request <= 1'b0; end else begin // Set down request, as we are not request pipelining request <= 1'b0; // We can be WrDAck'ed at this time p.29 or WrBTerm p.30 if(mWrBTerm == 1) begin wrBurst <= 1'b0; end else if(mWrDAck == 1) begin storeDataCount <= newstoreDataCount; storeDataCount_plus2 <= newstoreDataCount_plus2; stateStore <= Data; end else begin stateStore <= Data; end end end endrule rule storePage_Data(doingStore && stateStore == Data); if((mWrBTerm == 1) && (storeDataCount_plus2 < (fromInteger(valueof(BeatsPerBurst)))) || (mErr == 1)) begin // We got terminated / Errored wrBurst <= 1'b0; storeDataCount <= 0; storeDataCount_plus2 <= 2; stateStore <= Idle; // Can't burst for a cycle p. 30 end else if(mWrDAck == 1) begin storeDataCount <= newstoreDataCount; storeDataCount_plus2 <= newstoreDataCount_plus2; if(newstoreDataCount == 0) begin //We're now done reading... what should we do? // Data transfer complete if(mBusy == 0) begin doingStore <= False; stateStore <= Idle; storeValid.deq(); storeCounter <= storeCounter + 1; end else begin stateStore <= WaitForBusy; end end else if(newstoreDataCount == maxBound) //YYY: used to be ~0 begin // Last read is upcoming. Need to set down the // wrBurst signal. wrBurst <= 1'b0; end end endrule rule storePage_WaitForBusy(doingStore && stateStore == WaitForBusy); if(mErr == 1) begin // We got terminated / Errored wrBurst <= 1'b0; storeDataCount <= 0; // may not be necessary storeDataCount_plus2 <= 2; stateStore <= Idle; // Can't burst for a cycle p. 30 end else if(mBusy == 0) begin storeCounter <= storeCounter + 1; doingStore <= False; stateStore <= Idle; storeValid.deq(); end endrule /******** /* Code For Handling Record Translation /*******/ Reg#(Bit#(DoubleWordWidth)) recordSled <- mkReg(0); rule writeStoreData(storeValid.notFull()); storeBufferWritePointer <= storeBufferWritePointer + 1; case(storeBufferWritePointer[0]) 0: storeBuffer.upd(storeBufferWritePointer, {recordInfifo.first[31:0] ,recordInfifo.first[63:32]}); 1: storeBuffer.upd(storeBufferWritePointer, {recordInfifo.first[95:64],recordInfifo.first[127:96]}); endcase if((storeBufferWritePointer + 1)[0] == 0) begin recordInfifo.deq; end Bit#(TLog#(BeatsPerBurst)) bottomValue = 0; if(truncate(storeBufferWritePointer + 1) == bottomValue) begin $display("Store Data finished a flight"); storeValid.enq(0); end endrule rule wordToRecord(loadValid.notEmpty()); loadBufferReadPointer <= loadBufferReadPointer + 1; Bit#(64) loadValue = loadBuffer.sub(loadBufferReadPointer); Bit#(32) loadHigh = loadValue [63:32]; Bit#(32) loadLow = loadValue [31:0]; Bit#(TLog#(BeatsPerBurst)) bottomValue = 0; if(truncate(loadBufferReadPointer + 1) == bottomValue) begin $display("Load Data finished a flight"); loadValid.deq(); end if((loadBufferReadPointer + 1)[0] == 0) begin recordOutfifo.enq({{loadLow,loadHigh},recordSled}); end else begin recordSled <= {loadLow,loadHigh}; end endrule interface Put wordInput = fifoToPut(recordInfifo); interface Get wordOutput = fifoToGet(recordOutfifo); interface Put plbMasterCommandInput = fifoToPut(plbMasterCommandInfifo); interface PLBMasterWires plbMasterWires; method Bit#(PLBAddrSize) mABus(); // Address Bus return mABus_o; endmethod method Bit#(8) mBE(); // Byte Enable return mBE_o; endmethod method Bit#(1) mRNW(); // Read Not Write return mRNW_o; endmethod method Bit#(1) mAbort(); // Abort return mAbort_o; endmethod method Bit#(1) mBusLock(); // Bus lock return mBusLock_o; endmethod method Bit#(1) mCompress(); // compressed transfer return mCompress_o; endmethod method Bit#(1) mGuarded(); // guarded transfer return mGuarded_o; endmethod method Bit#(1) mLockErr(); // lock error return mLockErr_o; endmethod method Bit#(2) mMSize(); // data bus width? return mMSize_o; endmethod method Bit#(1) mOrdered(); // synchronize transfer return mOrdered_o; endmethod method Bit#(2) mPriority(); // priority indicator return mPriority_o; endmethod method Bit#(1) mRdBurst(); // read burst return mRdBurst_o; endmethod method Bit#(1) mRequest(); // bus request return mRequest_o; endmethod method Bit#(4) mSize(); // transfer size return mSize_o; endmethod method Bit#(3) mType(); // transfer type (dma) return mType_o; endmethod method Bit#(1) mWrBurst(); // write burst return mWrBurst_o; endmethod method Bit#(64) mWrDBus(); // write data bus return mWrDBus_o; endmethod method Action plbIN( Bit#(1) mRst_in, // PLB reset Bit#(1) mAddrAck_in, // Addr Ack Bit#(1) mBusy_in, // Master Busy Bit#(1) mErr_in, // Slave Error Bit#(1) mRdBTerm_in, // Read burst terminate signal Bit#(1) mRdDAck_in, // Read data ack Bit#(64)mRdDBus_in, // Read data bus Bit#(3) mRdWdAddr_in, // Read word address Bit#(1) mRearbitrate_in, // Rearbitrate Bit#(1) mWrBTerm_in, // Write burst terminate Bit#(1) mWrDAck_in, // Write data ack Bit#(1) mSSize_in, // Slave bus size Bit#(1) sMErr_in, // Slave error Bit#(1) sMBusy_in); // Slave busy mRst <= mRst_in; mAddrAck <= mAddrAck_in; mBusy <= mBusy_in; mErr <= mErr_in; mRdBTerm <= mRdBTerm_in; mRdDAck <= mRdDAck_in; mRdDBus <= mRdDBus_in; mRdWdAddr <= mRdWdAddr_in; mRearbitrate <= mRearbitrate_in; mWrBTerm <= mWrBTerm_in; mWrDAck <= mWrDAck_in; mSSize <= mSSize_in; sMErr <= sMErr_in; sMBusy <= sMBusy_in; endmethod endinterface endmodule 1.1 cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMasterBackup.bsv http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMasterBackup.bsv?rev=1.1&content-type=text/x-cvsweb-markup Index: PLBMasterBackup.bsv =================================================================== /* Copyright (c) 2007 MIT Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Author: Kermin Fleming */ import BRAM::*; import BRAMInitiatorWires::*; import GetPut::*; import FIFO::*; import FIFOF::*; import Types::*; import Interfaces::*; import Parameters::*; import DebugFlags::*; import BRAMInitiator::*; typedef 128 DataSize; (* synthesize *) module mkPLBMasterBackup( PLBMasterBackup ); FIFO#(ComplexWord) wordOutfifo <- mkFIFO; FIFO#(ComplexWord) wordInfifo <- mkFIFO; FIFO#(PLBMasterCommand) plbMasterCommandInfifo <- mkFIFO(); let bufferSize = 129; // use extra space for a flag let minLoadPtrA = 0; let maxLoadPtrA = minLoadPtrA + bufferSize; let minLoadPtrB = maxLoadPtrA + bufferSize; let maxLoadPtrB = minLoadPtrB + bufferSize; let minStorePtrA = maxLoadPtrB + bufferSize; let maxStorePtrA = minStorePtrA + bufferSize; let minStorePtrB = maxStorePtrA + bufferSize; let maxStorePtrB = minStorePtrB + bufferSize; let ready = True; let debugF = debug(feederDebug); Reg#(Bit#(14)) readPtr <- mkReg(minLoadPtrA); Reg#(Bit#(14)) writePtr <- mkReg(minStorePtrA); Reg#(FeederState) state <- mkReg(FI_InStartCheckRead); Reg#(Bit#(32)) partialRead <- mkReg(0); Reg#(Bool) doingLoad <- mkReg(False); Reg#(Bool) doingStore <- mkReg(False); Reg#(Bool) loadBufferA <- mkReg(True); Reg#(Bool) storeBufferA <- mkReg(True); Reg#(Bit#(TLog#(DataSize))) count <- mkReg(0); Reg#(Bit#(TSub#(LogBlockElements,(TLog#(DataSize))))) rotations <- mkReg(0); BRAMInitiator#(Bit#(14)) bramInit <- mkBRAMInitiator; let bram = bramInit.bram; rule inWaitCommand(ready && state == FI_command); begin rotations <= 0; case (plbMasterCommandInfifo.first()) matches tagged RowSize .rs: begin plbMasterCommandInfifo.deq(); end tagged LoadPage .ba: begin plbMasterCommandInfifo.deq(); state <= FI_InStartCheckRead; readPtr <= 0; if(loadBufferA) begin bram.read_req(minLoadPtrA); end else begin bram.read_req(minLoadPtrB); end end tagged StorePage .ba: begin plbMasterCommandInfifo.deq(); doingStore <= True; state <= FI_OutStartCheckWrite; writePtr <= 0; if(storeBufferA) begin bram.read_req(minStorePtrA); end else begin bram.read_req(minStorePtrB); end end default: $display("Illegal command for PLB Master"); endcase end endrule rule inStartCheckRead(ready && state == FI_InStartCheckRead); debugF($display("BRAM: StartCheckRead")); let v <- bram.read_resp(); if(v != 0) begin state <= FI_InStartRead; if(loadBufferA) begin readPtr <= 2; bram.read_req(minLoadPtrA + 1); end else begin readPtr <= 2; bram.read_req(minLoadPtrB + 1); end end else begin if(loadBufferA) begin bram.read_req(minLoadPtrA); end else begin bram.read_req(minLoadPtrB); end end endrule rule inStartRead(ready && state == FI_InStartRead); let v <- bram.read_resp(); wordOutfifo.enq(unpack(v)); readPtr <= readPtr + 1; count <= count + 1; if(count+1 == 0) begin rotations <= rotations + 1; if(rotations + 1 == 0) begin state <= FI_command; loadBufferA <= True; end else begin loadBufferA <= !loadBufferA; end if(loadBufferA) begin bram.write(minLoadPtrA,0); end else begin bram.write(minLoadPtrB,0); end end else if(loadBufferA) begin bram.read_req(minLoadPtrA + readPtr); end else begin bram.read_req(minLoadPtrB + readPtr); end debugF($display("BRAM: StartRead %h", v)); endrule rule inStartCheckWrite(ready && state == FI_OutStartCheckWrite); debugF($display("BRAM: StartCheckWrite")); let v <- bram.read_resp(); if(v == 0) begin state <= FI_OutStartWrite; writePtr <= 1; end else begin if(storeBufferA) begin bram.read_req(minStorePtrA); end else begin bram.read_req(minStorePtrB); end end endrule rule inStartWrite(ready && state == FI_OutStartWrite); debugF($display("BRAM: StartWrite")); $display("BRAM: write [%d] = %h",writePtr+1, wordInfifo.first); writePtr <= writePtr + 1; count <= count + 1; if(count+1 == 0) begin rotations <= rotations + 1; if(rotations + 1 == 0) begin state <= FI_OutStartPush; end else begin storeBufferA <= !storeBufferA; end if(storeBufferA) begin bram.write(writePtr+minStorePtrA, truncate(pack(wordInfifo.first()))); end else begin bram.write(writePtr+minStorePtrB, truncate(pack(wordInfifo.first()))); end wordInfifo.deq(); end endrule rule inStartPush(ready && state == FI_OutStartPush); storeBufferA <= True; if(storeBufferA) begin bram.write(minStorePtrA, ~0); end else begin bram.write(minStorePtrB, ~0); end state <= FI_command; endrule interface Put wordInput = interface Put; method Action put(x); wordInfifo.enq(x); //$display("PLB: got val %h", x); endmethod endinterface; interface Get wordOutput = interface Get; method get(); actionvalue //$display("PLB: sending val %h", wordOutfifo.first()); wordOutfifo.deq(); return wordOutfifo.first(); endactionvalue endmethod endinterface; interface Put plbMasterCommandInput = fifoToPut(plbMasterCommandInfifo); interface plbBRAMWires = bramInit.bramInitiatorWires; endmodule 1.1 cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMasterDummy.bsv http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMasterDummy.bsv?rev=1.1&content-type=text/x-cvsweb-markup Index: PLBMasterDummy.bsv =================================================================== import RegFile ::*; import Interfaces ::*; import Types ::*; import Memocode08Types ::*; import Parameters ::*; import FIFO ::*; import GetPut ::*; import Connectable ::*; import Memocode08Types ::*; `define DummyDebug False module mkPLBMasterDummy(PLBMaster); Reg#(Bit#(5)) stall <- mkReg(~0); Reg#(Bit#(2)) jitter1 <- mkReg(0); Reg#(Bit#(1)) jitter2 <- mkReg(1); BlockAddr bank_mask = (fromInteger(valueOf(MemBankSelector))>>2); RegFile#(Bit#(18), Record) mem_hi <- mkRegFileFull(); RegFile#(Bit#(18), Record) mem_lo <- mkRegFileFullLoad("unsorted.hex"); Reg#(BlockAddr) plbMasterCount <- mkReg(0); FIFO#(PLBMasterCommand) stall_fifo <- mkFIFO(); FIFO#(PLBMasterCommand) plbMasterCommand <- mkFIFO(); function Tuple2#(Bool,BlockAddr) m(PLBMasterCommand a); if (a matches tagged LoadPage .addr) return tuple2(True,addr); else return tuple2(False,?); endfunction rule toggle (True); jitter1 <= jitter1-1; jitter2 <= jitter2-1; endrule rule decr_stall (stall != 0); stall <= stall-1; endrule rule xfer (stall==0); plbMasterCommand.enq(stall_fifo.first()); stall_fifo.deq(); stall <= maxBound; endrule interface Put wordInput; method Action put(Record wordInput) if(plbMasterCommand.first matches (tagged StorePage .addr) &&& (jitter1==0)); let mem = ((addr&bank_mask)!=0) ? mem_hi : mem_lo; let idx = (addr>>2) + plbMasterCount; mem.upd(truncate(pack(idx)), wordInput); if(`DummyDebug) $display("plbMaster put %d", plbMasterCount); if(plbMasterCount + 1 == fromInteger(valueOf(RecordsPerMemRequest))) begin plbMasterCommand.deq; plbMasterCount <= 0; end else begin plbMasterCount <= plbMasterCount + 1; end if(`DummyDebug) $display("%m call put with addr %x mask %x",addr, addr&bank_mask); endmethod endinterface // using this function m is ugly, but I can't get the damn match syntax to parse // correctly inthe rule predicate... FUCK! interface Get wordOutput; method ActionValue#(Record) get() if(plbMasterCommand.first matches (tagged LoadPage .addr) &&& (jitter2==0)); let mem = ((addr&bank_mask)!=0) ? mem_hi : mem_lo; let idx = (addr>>2) + plbMasterCount; let rv = mem.sub(truncate(pack(idx))); if(`DummyDebug) $display("plbMaster get %d", plbMasterCount); if(`DummyDebug) $display("%m call get with addr %x mask %x",addr, addr&bank_mask); if(plbMasterCount + 1 == fromInteger(valueOf(RecordsPerMemRequest))) begin plbMasterCommand.deq; plbMasterCount <= 0; end else begin plbMasterCount <= plbMasterCount + 1; end return rv; endmethod endinterface interface Put plbMasterCommandInput; method Action put(PLBMasterCommand command); if(command matches tagged LoadPage .addr) begin if(`DummyDebug) $display("plbMasterCommand load %h", addr); end else if(command matches tagged StorePage .addr) begin if(`DummyDebug) $display("plbMasterCommand store %h", addr); end else $error(); stall_fifo.enq(command); endmethod endinterface interface plbMasterWires = ?; endmodule 1.1 cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMasterMagic.bsv http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMasterMagic.bsv?rev=1.1&content-type=text/x-cvsweb-markup Index: PLBMasterMagic.bsv =================================================================== /* Copyright (c) 2007 MIT Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Author: Kermin Fleming */ // Global Imports import GetPut::*; import FIFO::*; import RegFile::*; // Project Imports `include "Common.bsv" import PLBMasterWires::*; typedef enum { Test, Sleep, Finish } TestState deriving(Bits, Eq); (* synthesize *) module mkPLBMasterMagic (PLBMaster); // state for the actual magic memory hardware FIFO#(ComplexWord) wordInfifo <- mkFIFO(); FIFO#(ComplexWord) wordOutfifo <- mkFIFO(); FIFO#(PLBMasterCommand) plbMasterCommandInfifo <- mkFIFO(); RegFile#(Bit#(20), ComplexWord) matrixA <- mkRegFileFullLoad("matrixA.hex"); RegFile#(Bit#(20), ComplexWord) matrixB <- mkRegFileFullLoad("matrixB.hex"); RegFile#(Bit#(20), ComplexWord) matrixC <- mkRegFileFull(); RegFile#(Bit#(20), ComplexWord) scratch <- mkRegFileFull(); Reg#(Bit#(LogBlockElements)) elementCounter <- mkReg(0); Reg#(Bit#(LogBlockSize)) rowCounter <- mkReg(0); // 0 -> blocksize Reg#(Bit#(LogRowSize)) rowOffset <- mkReg(0); Reg#(BlockAddr) addressOffset <- mkReg(0); // State for running the golden test loop RegFile#(Bit#(20), ComplexWord) golden <- mkRegFileFullLoad("golden.hex"); Reg#(Bit#(32)) goldenElementCounter <- mkReg(0); Reg#(Bit#(64)) totalTicks <- mkReg(0); rule tick(True); totalTicks <= totalTicks +1; endrule rule rowSize(plbMasterCommandInfifo.first() matches tagged RowSize .rs); debug(plbMasterDebug, $display("PLBMaster: processing RowSize command %d", rs)); rowOffset <= rs; plbMasterCommandInfifo.deq(); endrule rule loadPage(plbMasterCommandInfifo.first() matches tagged LoadPage .ba); elementCounter <= elementCounter + 1; if(elementCounter == 0) begin debug(plbMasterDebug, $display("PLBMaster: processing LoadPage command")); end if(elementCounter + 1 == 0) begin debug(plbMasterDebug, $display("PLBMaster: finished LoadPage command")); addressOffset <= 0; rowCounter <= 0; plbMasterCommandInfifo.deq(); end else if(rowCounter + 1 == 0) begin //When we get to the end of a row, we need to reset by //shifting the Address Offset to 1 row higher = rowCounter <= 0; addressOffset <= addressOffset + 1 - unpack(fromInteger(1*valueof(BlockSize))) + (1 << rowOffset); end else begin addressOffset <= addressOffset + 1; rowCounter <= rowCounter + 1; end BlockAddr addr = ba + addressOffset; // Now that we're done with calculating the address, // we can case out our memory space //case (addr[23:22]) // 2'b00: begin $display("PLB: reading matA[%h] => %h" ,addr[21:2], matrixA.sub(addr[21:2])); end // 2'b01: begin $display("PLB: reading matB[%h] => %h" ,addr[21:2], matrixB.sub(addr[21:2])); end // 2'b10: begin $display("PLB: reading matC[%h] => %h" ,addr[21:2], matrixC.sub(addr[21:2])); end // 2'b11: begin $display("PLB: reading scratch[%h] => %h",addr[21:2], scratch.sub(addr[21:2])); end //endcase case (addr[21:20]) 2'b00: wordOutfifo.enq(matrixA.sub(addr[19:0])); 2'b01: wordOutfifo.enq(matrixB.sub(addr[19:0])); 2'b10: wordOutfifo.enq(matrixC.sub(addr[19:0])); 2'b11: wordOutfifo.enq(scratch.sub(addr[19:0])); endcase endrule rule storePage(plbMasterCommandInfifo.first() matches tagged StorePage .ba); elementCounter <= elementCounter + 1; if(elementCounter == 0) begin debug(plbMasterDebug, $display("PLBMaster: processing StorePage command")); end if(elementCounter + 1 == 0) begin debug(plbMasterDebug, $display("PLBMaster: finished StorePage command")); addressOffset <= 0; rowCounter <= 0; plbMasterCommandInfifo.deq(); end else if(rowCounter + 1 == 0) begin addressOffset <= addressOffset + 1 - unpack(fromInteger(valueof(BlockSize))) + (1 << rowOffset); rowCounter <= 0; end else begin addressOffset <= addressOffset + 1; rowCounter <= rowCounter + 1; end BlockAddr addr = ba + addressOffset; // Now that we're done with calculating the address, // we can case out our memory space case (addr[21:20]) 2'b00: begin debug(plbMasterDebug,$display("PLB: writing to matA %h",addr[19:0])); matrixA.upd(addr[19:0],wordInfifo.first()); end 2'b01: begin debug(plbMasterDebug,$display("PLB: writing to matB %h",addr[19:0])); matrixB.upd(addr[19:0],wordInfifo.first()); end 2'b10: begin debug(plbMasterDebug,$display("PLB: writing to matC %h",addr[19:0])); matrixC.upd(addr[19:0],wordInfifo.first()); let oldval = matrixC.sub(addr[19:0]); let goldenval = golden.sub(addr[19:0]); if ((goldenval != oldval) && (goldenval == wordInfifo.first())) // a new correct val begin goldenElementCounter <= goldenElementCounter +1; if (truncate(goldenElementCounter) == 16'hFFFF) // time to announce $display("Correct Value Count: %d @ %d", goldenElementCounter+1,totalTicks); if (goldenElementCounter + 1 == (1 << (rowOffset<<1))) begin $display("PASSED @ %d", totalTicks); $finish; end end end 2'b11: begin debug(plbMasterDebug,$display("PLB: writing to scratch %h",addr[19:0])); scratch.upd(addr[19:0],wordInfifo.first()); end endcase wordInfifo.deq(); endrule rule debugRule (True); case (plbMasterCommandInfifo.first()) matches tagged LoadPage .i: noAction; tagged StorePage .i: noAction; tagged RowSize .sz: noAction; default: $display("PLBMaster: illegal command: %h", plbMasterCommandInfifo.first()); endcase endrule interface Put wordInput = interface Put; method Action put(x); wordInfifo.enq(x); //$display("PLB: got val %h", x); endmethod endinterface; interface Get wordOutput = interface Get; method get(); actionvalue //$display("PLB: sending val %h", wordOutfifo.first()); wordOutfifo.deq(); return wordOutfifo.first(); endactionvalue endmethod endinterface; interface Put plbMasterCommandInput = fifoToPut(plbMasterCommandInfifo); interface PLBMasterWires plbMasterWires = ?; endmodule 1.1 cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMasterTester.bsv http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMasterTester.bsv?rev=1.1&content-type=text/x-cvsweb-markup Index: PLBMasterTester.bsv =================================================================== /* Copyright (c) 2008 MIT Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Author: Kermin Fleming */ import PLBMasterWires::*; import BRAMInitiatorWires::*; import PLBMaster::*; import BRAMFeeder::*; import Interfaces::*; import Parameters::*; import FIFO::*; import GetPut::*; import Types::*; import Memocode08Types::*; interface PLBMasterTester; interface PLBMasterWires plbMasterWires; interface BRAMInitiatorWires#(Bit#(14)) bramInitiatorWires; endinterface typedef enum{ Idle, Running, Inputing, Outputing } TesterState deriving (Bits,Eq); module mkPLBMasterTester(PLBMasterTester); Feeder feeder <- mkBRAMFeeder(); PLBMaster plbMaster <- mkPLBMaster; Reg#(TesterState) state <- mkReg(Idle); Reg#(BlockAddr) baseRegLoad <- mkReg(0); Reg#(BlockAddr) baseRegStore <- mkReg(0); Reg#(Bit#(19)) commandCount <- mkReg(0); Reg#(Bit#(32)) commandsComplete <- mkReg(1); FIFO#(Record) dataFIFO <- mkSizedFIFO(32); Reg#(Bool) evenZero <- mkReg(True); rule grabInstruction(state == Idle); PPCMessage inst <- feeder.ppcMessageOutput.get; baseRegLoad <= truncate(pack(inst)); baseRegStore <= truncate(pack(inst)); state <= Running; endrule rule issueCommand(state == Running); commandCount <= commandCount + 1; if(commandCount + 1 == 0) begin state <= Idle; feeder.ppcMessageInput.put(pack(commandsComplete)); commandsComplete <= commandsComplete + 1; end if(commandCount[2] == 0) begin baseRegLoad <= baseRegLoad + fromInteger(valueof(TMul#(BeatsPerBurst,WordsPerBeat))); plbMaster.plbMasterCommandInput.put(tagged LoadPage (baseRegLoad)); end else begin baseRegStore <= baseRegStore + fromInteger(valueof(TMul#(BeatsPerBurst,WordsPerBeat))); plbMaster.plbMasterCommandInput.put(tagged StorePage (baseRegStore)); end endrule rule inputing; Record data <- plbMaster.wordOutput.get; dataFIFO.enq(data); endrule rule outputing; plbMaster.wordInput.put(unpack((~(pack(dataFIFO.first))) & (~1))); dataFIFO.deq; endrule interface plbMasterWires = plbMaster.plbMasterWires; interface bramInitiatorWires = feeder.bramInitiatorWires; endmodule 1.1 cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMasterWires.bsv http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMasterWires.bsv?rev=1.1&content-type=text/x-cvsweb-markup Index: PLBMasterWires.bsv =================================================================== /* Copyright (c) 2007 MIT Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Author: Kermin Fleming */ // Global Imports import GetPut::*; // Project Imports import Parameters::*; `define PLB_CLK_NAME "mClk" `define PLB_RST_NAME "mRst" `define PLB_COMPRESS_NAME "mCompress" `define PLB_ABUS_NAME "mABus" `define PLB_BE_NAME "mBE" `define PLB_RNW_NAME "mRNW" `define PLB_ABORT_NAME "mAbort" `define PLB_BUSLOCK_NAME "mBusLock" `define PLB_PRESS_NAME "mpress" `define PLB_GUARDED_NAME "mGuarded" `define PLB_LOCKERR_NAME "mLockErr" `define PLB_MSIZE_NAME "mMSize" `define PLB_ORDERED_NAME "mOrdered" `define PLB_PRIORITY_NAME "mPriority" `define PLB_RDBURST_NAME "mRdBurst" `define PLB_REQUEST_NAME "mRequest" `define PLB_SIZE_NAME "mSize" `define PLB_TYPE_NAME "mType" `define PLB_WRBURST_NAME "mWrBurst" `define PLB_WRDBUS_NAME "mWrDBus" `define PLB_MADDRACK_NAME "mAddrAck" `define PLB_MBUSY_NAME "mBusy" `define PLB_MERR_NAME "mErr" `define PLB_MRDBTERM_NAME "mRdBTerm" `define PLB_MRDDACK_NAME "mRdDAck" `define PLB_MRDDBUS_NAME "mRdDBus" `define PLB_MRDWDADDR_NAME "mRdWdAddr" `define PLB_MREARBITRATE_NAME "mRearbitrate" `define PLB_MWRBTERM_NAME "mWrBTerm" `define PLB_MWRDACK_NAME "mWrDAck" `define PLB_MSSIZE_NAME "mSSize" `define PLB_SMERR_NAME "sMErr" `define PLB_SMBUSY_NAME "sMBusy" interface PLBMasterWires; (* always_ready, prefix="", result=`PLB_ABUS_NAME *) method Bit#(PLBAddrSize) mABus(); // Address Bus (* always_ready, prefix="", result=`PLB_BE_NAME *) method Bit#(8) mBE(); // Byte Enable (* always_ready, prefix="", result=`PLB_RNW_NAME *) method Bit#(1) mRNW(); // Read Not Write (* always_ready, prefix="", result=`PLB_ABORT_NAME *) method Bit#(1) mAbort(); // Abort (* always_ready, prefix="", result=`PLB_BUSLOCK_NAME *) method Bit#(1) mBusLock(); // Bus lock (* always_ready, prefix="", result=`PLB_COMPRESS_NAME *) method Bit#(1) mCompress(); // compressed transfer (* always_ready, prefix="", result=`PLB_GUARDED_NAME *) method Bit#(1) mGuarded(); // guarded transfer (* always_ready, prefix="", result=`PLB_LOCKERR_NAME *) method Bit#(1) mLockErr(); // lock error (* always_ready, prefix="", result=`PLB_MSIZE_NAME *) method Bit#(2) mMSize(); // data bus width? (* always_ready, prefix="", result=`PLB_ORDERED_NAME *) method Bit#(1) mOrdered(); // synchronize transfer (* always_ready, prefix="", result=`PLB_PRIORITY_NAME *) method Bit#(2) mPriority(); // priority indicator (* always_ready, prefix="", result=`PLB_RDBURST_NAME *) method Bit#(1) mRdBurst(); // read burst (* always_ready, prefix="", result=`PLB_REQUEST_NAME *) method Bit#(1) mRequest(); // bus request (* always_ready, prefix="", result=`PLB_SIZE_NAME *) method Bit#(4) mSize(); // transfer size (* always_ready, prefix="", result=`PLB_TYPE_NAME *) method Bit#(3) mType(); // transfer type (dma) (* always_ready, prefix="", result=`PLB_WRBURST_NAME *) method Bit#(1) mWrBurst(); // write burst (* always_ready, prefix="", result=`PLB_WRDBUS_NAME *) method Bit#(64) mWrDBus(); // write data bus (* always_ready, prefix="", always_enabled *) method Action plbIN( (* port=`PLB_RST_NAME *) Bit#(1) mRst, // PLB reset (* port=`PLB_MADDRACK_NAME *) Bit#(1) mAddrAck, // Addr Ack (* port=`PLB_MBUSY_NAME *) Bit#(1) mBusy, // Master Busy (* port=`PLB_MERR_NAME *) Bit#(1) mErr, // Slave Error (* port=`PLB_MRDBTERM_NAME *) Bit#(1) mRdBTerm, // Read burst terminate signal (* port=`PLB_MRDDACK_NAME *) Bit#(1) mRdDAck, // Read data ack (* port=`PLB_MRDDBUS_NAME *) Bit#(64)mRdDBus, // Read data bus (* port=`PLB_MRDWDADDR_NAME *) Bit#(3) mRdWdAddr, // Read word address (* port=`PLB_MREARBITRATE_NAME *) Bit#(1) mRearbitrate, // Rearbitrate (* port=`PLB_MWRBTERM_NAME *) Bit#(1) mWrBTerm, // Write burst terminate (* port=`PLB_MWRDACK_NAME *) Bit#(1) mWrDAck, // Write data ack (* port=`PLB_MSSIZE_NAME *) Bit#(1) mSSize, // Slave bus size (* port=`PLB_SMERR_NAME *) Bit#(1) sMErr, // Slave error (* port=`PLB_SMBUSY_NAME *) Bit#(1) sMBusy); // Slave busy endinterface 1.1 cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMaster_backupPPC.bsv http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBMaster_backupPPC.bsv?rev=1.1&content-type=text/x-cvsweb-markup Index: PLBMaster_backupPPC.bsv =================================================================== /* Copyright (c) 2007 MIT Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Author: Kermin Fleming */ // Global Imports import GetPut::*; import FIFO::*; import RegFile::*; import BRAMInitiatorWires::*; import RegFile::*; import FIFOF::*; import BRAM::*; // Project Imports import Types::*; import Interfaces::*; import Parameters::*; import DebugFlags::*; import BRAMInitiator::*; import PLBMasterWires::*; import StmtFSM::*; (* synthesize *) module mkPLB_backupPPC(BRAMInitiatorWires#(Bit#(14))); RegFile#(Bit#(20), Bit#(32)) matrixA <- mkRegFileFullLoad("matrixA.hex"); RegFile#(Bit#(20), Bit#(32)) matrixB <- mkRegFileFullLoad("matrixB.hex"); RegFile#(Bit#(20), Bit#(32)) matrixC <- mkRegFileFull(); RegFile#(Bit#(20), Bit#(32)) scratch <- mkRegFileFull(); RegFile#(Bit#(20), Bit#(32)) golden <- mkRegFileFullLoad("golden.hex"); Reg#(Bit#(32)) goldenElementCounter <- mkReg(0); RegFile#(Bit#(16), Bit#(64)) prog <- mkRegFileFullLoad("program.hex"); Reg#(Bit#(16)) prog_idx <- mkReg(0); //State BRAMInitiator#(Bit#(14)) bramInit <- mkBRAMInitiator; let bram = bramInit.bram; //BRAM#(Bit#(14), Bit#(32)) bram <- mkBRAM_Full(); FIFOF#(Bit#(32)) outQ <- mkFIFOF(); FIFO#(Bit#(32)) inQ <- mkFIFO(); FIFO#(Bit#(64)) commandQ <- mkFIFO(); Reg#(Bit#(30)) baseAddr <- mkRegU; let minWritePtr = 0; let maxWritePtr = 129*2-1; let minReadPtr = 129*2; let maxReadPtr = 129*4-1; let burstSize = 128; Reg#(Bit#(14)) readPtr <- mkReg(minReadPtr); Reg#(Bit#(14)) writePtr <- mkReg(minWritePtr); let incWritePtr = (writePtr == maxWritePtr) ? minWritePtr : (writePtr + 1); let incReadPtr = (readPtr == maxReadPtr) ? minReadPtr : (readPtr + 1); let ready = True; let debugF = debug(False); Reg#(Bit#(10)) count <- mkReg(0); Reg#(Bit#(32)) value <- mkReg(0); Reg#(Bit#(64)) totalTicks <- mkReg(0); Reg#(Bit#(32)) rowOffset <- mkReg(0); // stored in terms of words function Action readAddr(addr); case (addr[21:20]) 2'b00: return (matrixA.sub(addr[19:0])); 2'b01: return (matrixB.sub(addr[19:0])); 2'b10: return (matrixC.sub(addr[19:0])); 2'b11: return (scratch.sub(addr[19:0])); endcase endfunction function Action writeAddr(addr,val); action case (addr[21:20]) 2'b00: begin debugF($display("PLB: writing to matA %h",addr[19:0])); matrixA.upd(addr[19:0],val); end 2'b01: begin debugF($display("PLB: writing to matB %h",addr[19:0])); matrixB.upd(addr[19:0],val); end 2'b10: begin debugF($display("PLB: writing to matC %h",addr[19:0])); matrixC.upd(addr[19:0],val); let oldval = matrixC.sub(addr[19:0]); let goldenval = golden.sub(addr[19:0]); if ((goldenval != oldval) && (goldenval == val)) // a new correct val begin goldenElementCounter <= goldenElementCounter +1; if (truncate(goldenElementCounter) == 16'hFFFF) // time to announce $display("Correct Value Count: %d @ %d", goldenElementCounter+1,totalTicks); if (goldenElementCounter + 1 == (rowOffset * rowOffset)) begin $display("PASSED @ %d", totalTicks); $finish; end end end 2'b11: begin debugF($display("PLB: writing to scratch %h",addr[19:0])); scratch.upd(addr[19:0],val); end endcase endaction endfunction /////////////////////////////////////////////////////////// // In goes to MEM, Out goes back to FPGA /////////////////////////////////////////////////////////// Stmt doReadStmt = seq bram.read_req(readPtr); action let v <- bram.read_resp(); value <= v; count <= 0; endaction if (value != 0) seq while(count < burstSize) seq action readPtr <= incReadPtr; count <= count + 1; let v <- bram.read_resp(); writeAddr(baseAddr+zeroExtend(count), v); if (count <burstSize) bram.read_req(readPtr+1); // if (count == burstSize) bram.write(readPtr - burstSize, 0); // take endaction endseq endseq endseq; FSM doRead <- mkFSM(doReadStmt); Stmt doWriteStmt = seq bram.read_req(writePtr); action let v <- bram.read_resp(); value <= v; count <= 0; endaction if (value == 0) seq while(count < burstSize) seq action writePtr <= incWritePtr; count <= count + 1; if (count <burstSize) begin let val = readAddr(baseAddr+zeroExtend(count)); bram.write(writePtr+1, val); // end if (count == burstSize) bram.write(writePtr - burstSize, 32'hFFFFFFFF); // take endaction endseq endseq commandQ.deq(); endseq; FSM doWrite <- mkFSM(doWriteStmt); rule doStuff(doRead.done && doWrite.done); let inst = unpack(truncate(commandQ.first)); let mload = translateLoad(inst); let mstore = translateStore(inst); let mrow = translateRowSize(inst); commandQ.deq(); if (isJust(mload)) begin baseAddr <= unJust(mload); doRead.start(); end else if (isJust(mstore)) begin baseAddr <= unJust(mstore); doWrite.start(); end else if (isJust(mrow)) begin rowOffset <= zeroExtend(unJust(mrow)); end endrule rule tick(True); totalTicks <= totalTicks +1; endrule rule doProgRead(prog.sub(prog_idx) != 64'hAAAA_AAAA_AAAA_AAAA); let x = prog.sub(prog_idx); commandQ.enq(x); prog_idx <= prog_idx + 1; endrule return (bramInit.bramInitiatorWires); endmodule 1.1 cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBModel.bsv http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBModel.bsv?rev=1.1&content-type=text/x-cvsweb-markup Index: PLBModel.bsv =================================================================== /* Copyright (c) 2007 MIT Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Author: Kermin Fleming */ import Types::*; import Parameters::*; import Interfaces::*; import DebugFlags::*; import PLBMasterWires::*; import RegFile::*; module mkPLBModel#(PLBMasterWires plb) (); RegFile#(Bit#(20), Bit#(32)) matrixA <- mkRegFileFullLoad("invert.hex"); RegFile#(Bit#(20), Bit#(32)) matrixB <- mkRegFileFull(); RegFile#(Bit#(20), Bit#(32)) matrixC <- mkRegFileFull(); RegFile#(Bit#(20), Bit#(32)) scratch <- mkRegFileFull(); Reg#(Bit#(PLBAddrSize)) curAddr <- mkReg(0); Reg#(Bit#(8)) transferSize <- mkReg(0); Reg#(Bit#(32)) wrValue <- mkReg(0); Reg#(Bool) doingRead <- mkReg(False); Reg#(Bool) doingWrite <- mkReg(False); Reg#(Maybe#(Bit#(64))) readValue <- mkReg(Nothing); Reg#(Bit#(PLBAddrSize)) mABus <- mkReg(0); Reg#(Bit#(8)) mBE <- mkReg(0); Reg#(Bool) mRNW <- mkReg(False); Reg#(Bit#(1)) mAbort <- mkReg(0); Reg#(Bit#(1)) mBusLock <- mkReg(0); Reg#(Bit#(1)) mCompress <- mkReg(0); Reg#(Bit#(1)) mGuarded <- mkReg(0); Reg#(Bit#(1)) mLockErr <- mkReg(0); Reg#(Bit#(2)) mMSize <- mkReg(0); Reg#(Bit#(1)) mOrdered <- mkReg(0); Reg#(Bit#(2)) mPriority <- mkReg(0); Reg#(Bool) mRdBurst <- mkReg(False); Reg#(Bool) mRequest <- mkReg(False); Reg#(Bit#(4)) mSize <- mkReg(0); Reg#(Bit#(3)) mType <- mkReg(0); Reg#(Bool) mWrBurst <- mkReg(False); Reg#(Bit#(64)) mWrDBus <- mkReg(0); // State for running the golden test loop Reg#(Bit#(32)) goldenElementCounter <- mkReg(0); Reg#(Bit#(64)) totalTicks <- mkReg(0); rule latch(True); mABus <= plb.mABus(); // Address Bus mBE <= plb.mBE(); // Byte Enable mRNW <= plb.mRNW() == 1; // Read Not Write mAbort <= plb.mAbort(); // Abort mBusLock <= plb.mBusLock(); // Bus lock mCompress <= plb.mCompress(); // compressed transfer mGuarded <= plb.mGuarded(); // guarded transfer mLockErr <= plb.mLockErr(); // lock error mMSize <= plb.mMSize(); // data bus width? mOrdered <= plb.mOrdered(); // synchronize transfer mPriority <= plb.mPriority(); // priority mRdBurst <= plb.mRdBurst() == 1; // read burst mRequest <= plb.mRequest() == 1; // bus request mSize <= plb.mSize(); // transfer size mType <= plb.mType(); // transfer type (dma) mWrBurst <= plb.mWrBurst() == 1; // write burst mWrDBus <= plb.mWrDBus(); // write data bus endrule rule doMagic(True); Bit#(1) plb_mRst = 0; // PLB reset Bit#(1) plb_mAddrAck = 0; // Addr Ack //* Bit#(1) plb_mBusy = 0; // Master Busy Bit#(1) plb_mErr = 0; // Slave Error Bit#(1) plb_mRdBTerm = 0; // Read burst terminate signal Bit#(1) plb_mRdDAck = 0; // Read data ack Bit#(64) plb_mRdDBus = 64'hcafefeeddeadbeef; // Read data bus Bit#(3) plb_mRdWdAddr = 0; // Read word address Bit#(1) plb_mRearbitrate = 0; // Rearbitrate Bit#(1) plb_mWrBTerm = 0; // Write burst terminate Bit#(1) plb_mWrDAck = 0; // Write data ack //* Bit#(1) plb_mSSize = 0; // Slave bus size Bit#(1) plb_sMErr = 0; // Slave error Bit#(1) plb_sMBusy = 0; //Terminating Previous Request // // Technically, it's "correct" for a burst of 1/2 // We're ignoring this if(transferSize == 1 && doingRead) // penultimate read begin plb_mRdBTerm = 1; // Read burst terminate signal end if(transferSize == 1 && doingWrite) plb_mWrBTerm = 1; //Determine if there's a new request // new read if mReq + mRNW + we've at just terminated or aren't working Bool newRead = mRequest && mRNW && (!doingRead || (plb_mRdBTerm ==1)); // new write if mReq + !mRNW + we've at hust terminated or aren't working Bool newWrite = mRequest && !mRNW && (!doingWrite || (plb_mWrBTerm ==1)); /////////////////////////////////////////////////////////////////// // // Read access logic. One cycle Delay // /////////////////////////////////////////////////////////////////// //Get Request //Bool newRead = !doingRead && mRequest && mRNW && !mWrBurst; //Bool newWrite = !doingWrite && mRequest && !mRNW && mWrBurst; plb_mAddrAck = pack(newRead || newWrite); plb_mWrDAck = pack(newWrite || doingWrite); Bool error_wrBurst_dropped_early = (transferSize > 1) && doingWrite && !mWrBurst; if (error_wrBurst_dropped_early) $display("ERROR: wrBurst dropped early"); if (newRead) transferSize <= mBE + 1; else if (newWrite) transferSize <= mBE +1; else if ((doingRead || doingWrite) && (transferSize > 0)) transferSize <= transferSize - 1; if (newRead || newWrite) curAddr <= mABus; else curAddr <= curAddr + 4; if (doingWrite) begin let wAddr = newWrite ? mABus : curAddr;//(curAddr + 4); let wData = (wAddr[2] == 0) ? mWrDBus[63:32]:mWrDBus[31:0]; case (wAddr[23:22]) 2'b00: begin debug(plbMasterDebug,$display("PLB: writing to matA %h",wAddr[21:2])); debug(plbMasterDebug,$display("PLB: got %h expected %h",wData, ~matrixA.sub( wAddr[21:2]))); if(wData != ~matrixA.sub( wAddr[21:2])) begin $finish; end matrixA.upd(wAddr[21:2],wData); end 2'b01: begin debug(plbMasterDebug,$display("PLB: writing to matB %h",wAddr[21:2])); $finish; end 2'b10: begin debug(plbMasterDebug,$display("PLB: writing to matC %h %h",wAddr[21:2],goldenElementCounter)); $finish; end 2'b11: begin debug(plbMasterDebug,$display("PLB: writing to scratch %h",wAddr[21:2])); $finish; end endcase end if(doingRead) case (curAddr[23:22]) 2'b00: readValue <= Just({matrixA.sub({curAddr[21:3],1}),(matrixA.sub({curAddr[21:3],0}))}); 2'b01: readValue <= Just({matrixB.sub({curAddr[21:3],1}),(matrixB.sub({curAddr[21:3],0}))}); 2'b10: readValue <= Just({matrixC.sub({curAddr[21:3],1}),(matrixC.sub({curAddr[21:3],0}))}); 2'b11: readValue <= Just({matrixC.sub({curAddr[21:3],1}),(matrixC.sub({curAddr[21:3],0}))}); endcase else readValue <= Nothing; plb_mRdDBus = case(readValue) matches tagged Nothing: return 64'hfeedcafedeadbeef; tagged Just .x: return x; endcase; plb_mRdDAck = isJust(readValue) ? 1 : 0; if (newRead) doingRead <= True; else if (transferSize == 1) doingRead <= False; if (newWrite) doingWrite <= True; else if (transferSize == 1) doingWrite <= False; /* if(transferSize == 1 && (doingRead || newRead)) // penultimate read begin plb_mRdBTerm = 1; // Read burst terminate signal end if(transferSize == 1 && (doingWrite || newWrite)) plb_mWrBTerm = 1; */ //wrComp and rdComp don't exist? plb.plbIN( plb_mRst, plb_mAddrAck, plb_mBusy, plb_mErr, plb_mRdBTerm, plb_mRdDAck, plb_mRdDBus, plb_mRdWdAddr, plb_mRearbitrate, plb_mWrBTerm, plb_mWrDAck, plb_mSSize, plb_sMErr, plb_sMBusy ); endrule endmodule 1.1 cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBSlave.bsv http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/PLBMaster/PLBSlave.bsv?rev=1.1&content-type=text/x-cvsweb-markup Index: PLBSlave.bsv =================================================================== /* Copyright (c) 2007 MIT Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Author: Kermin Fleming */ // Project Imports `include "Common.bsv" import PLBMasterWires::*; import RegFile::*; interface PLBSlave; interface PLBMasterWires plb; endinterface module mkPLBSlave#(PLBMastWires plb) (); RegFile#(Bit#(PLBAddrSize), Bit#(32)) rf <- mkRegFileFull(); Reg#(Bit#(PLBAddrSize)) curAddr <- mkReg(0); Reg#(Bit#(8)) transferSize <- mkReg(0); Reg#(Bit#(32)) wrValue <- mkReg(0); Reg#(Bool) doingRead <- mkReg(False); Reg#(Bool) doingWrite <- mkReg(False); Reg#(Maybe#(Bit#(32))) readValue <- mkReg(Nothing); Bit#(PLBAddrSize) mABus = plb.mABus(); // Address Bus Bit#(8) mBE = plb.mBE(); // Byte Enable Bool mRNW = plb.mRNW() == 1; // Read Not Write //Bit#(1) mAbort = plb.mAbort(); // Abort Bit#(1) mBusLock = plb.mBusLock(); // Bus lock //Bit#(1) mCompress = plb.mCompress(); // compressed transfer //Bit#(1) mGuarded = plb.mGuarded(); // guarded transfer //Bit#(1) mLockErr = plb.mLockErr(); // lock error Bit#(2) mMSize = plb.mMSize(); // data bus width? Bit#(1) mOrdered = plb.mOrdered(); // synchronize transfer //Bit#(2) mPriority = plb.mPriority(); // priority indicator Bool mRdBurst = plb.mRdBurst() == 1; // read burst Bool mRequest = plb.mRequest() == 1; // bus request Bit#(4) mSize = plb.mSize(); // transfer size //Bit#(3) mType = plb.mType(); // transfer type (dma) Bool mWrBurst = plb.mWrBurst() == 1; // write burst Bit#(32) mWrDBus = plb.mWrDBus(); // write data bus rule doMagic(True); Bit#(1) plb_mRst = 0; // PLB reset Bit#(1) plb_mAddrAck = 0; // Addr Ack //* Bit#(1) plb_mBusy = 0; // Master Busy Bit#(1) plb_mErr = 0; // Slave Error Bit#(1) plb_mRdBTerm = 0; // Read burst terminate signal Bit#(1) plb_mRdDAck = 1; // Read data ack Bit#(32) plb_mRdDBus = 32'hdeadbeef; // Read data bus Bit#(3) plb_mRdWdAddr = 0; // Read word address Bit#(1) plb_mRearbitrate = 0; // Rearbitrate Bit#(1) plb_mWrBTerm = 0; // Write burst terminate Bit#(1) plb_mWrDAck = 1; // Write data ack //* Bit#(1) plb_mSSize = 0; // Slave bus size Bit#(1) plb_sMErr = 0; // Slave error Bit#(1) plb_sMBusy = 0; //Get Request Bool newRead = mRequest && mRNW && mRdBurst && !mWrBurst; Bool newWrite = mRequest && !mRNW && !mRdBurst && mWrBurst; Bool error_Request = mRequest && !(newRead || newWrite); if (error_Request) $display("ERROR: poorly formatted request"); plb_mAddrAck = pack(newRead || newWrite); plb_mWrDAck = pack(newWrite || doingWrite); Bool error_wrBurst_dropped_early = (transferSize > 1) && doingWrite && !mWrBurst; if (error_wrBurst_dropped_early) $display("ERROR: wrBurst dropped early"); if (newRead) transferSize <= mBE + 1; else if (newWrite) transferSize <= mBE; else if (doingRead || doingWrite) transferSize <= transferSize - 1; if (newRead || newWrite) curAddr <= mABus; else curAddr <= curAddr + 1; if (newWrite) rf.upd(mABus, mWrDBus); else if (doingWrite) rf.upd(curAddr + 1, mWrDBus); if(doingRead) readValue <= Just(rf.sub(curAddr)); else readValue <= Nothing; plb_mRdDBus = case(readValue) matches tagged Nothing: return 32'hdeadbeef; tagged Just .x: return x; endcase; if (transferSize > 0) transferSize <= transferSize - 1; if (transferSize == 1) doingRead <= False; if (transferSize == 1) doingWrite <= False; if(transferSize == 2 && (doingRead || newRead)) // penultimate read begin plb_mRdBTerm = 1; // Read burst terminate signal end if(transferSize == 2 && (doingWrite || newWrite)) plb_mWrBTerm = 1; //wrComp and rdComp don't exist? plb.plbIN( plb_mRst, plb_mAddrAck, plb_mBusy, plb_mErr, plb_mRdBTerm, plb_mRdDAck, plb_mRdDBus, plb_mRdWdAddr, plb_mRearbitrate, plb_mWrBTerm, plb_mWrDAck, plb_mSSize, plb_sMErr, plb_sMBusy ); endrule endmodule 1.1 cryptosorter/memocodeDesignContest2008/xup/PLBMaster/mkPLBMaster.sched http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/PLBMaster/mkPLBMaster.sched?rev=1.1&content-type=text/x-cvsweb-markup Index: mkPLBMaster.sched =================================================================== === Generated schedule for mkPLBMaster === Method schedule --------------- Method: wordInput_put Ready signal: recordInfifo.i_notFull Conflict-free: wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Conflicts: wordInput_put Method: wordOutput_get Ready signal: recordOutfifo.i_notEmpty Conflict-free: wordInput_put, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Conflicts: wordOutput_get Method: plbMasterCommandInput_put Ready signal: plbMasterCommandInfifo.i_notFull Conflict-free: wordInput_put, wordOutput_get, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Conflicts: plbMasterCommandInput_put Method: plbMasterWires_mABus Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mBE Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mRNW Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mAbort Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mBusLock Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mCompress Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mGuarded Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mLockErr Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mMSize Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mOrdered Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mPriority Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mRdBurst Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus Sequenced after (restricted): plbMasterWires_plbIN Method: plbMasterWires_mRequest Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus Sequenced after (restricted): plbMasterWires_plbIN Method: plbMasterWires_mSize Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mType Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_mWrBurst Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus Sequenced after (restricted): plbMasterWires_plbIN Method: plbMasterWires_mWrDBus Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN Method: plbMasterWires_plbIN Ready signal: True Conflict-free: wordInput_put, wordOutput_get, plbMasterCommandInput_put, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrDBus Sequenced before (restricted): plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mWrBurst Conflicts: plbMasterWires_plbIN Rule schedule ------------- Rule: wordToRecord Predicate: ((loadBufferReadPointer + 5'd1)[0] || recordOutfifo.i_notFull) && loadValid.i_notEmpty Blocking rules: (none) Rule: writeStoreData Predicate: recordInfifo.i_notEmpty && storeValid.i_notFull Blocking rules: (none) Rule: storePage_WaitForBusy Predicate: doingStore && (stateStore == 2'd2) Blocking rules: (none) Rule: storePage_Data Predicate: doingStore && (stateStore == 2'd1) Blocking rules: (none) Rule: storePage_Requesting Predicate: doingStore && (stateRequest == 2'd2) && (stateStore == 2'd0) Blocking rules: (none) Rule: storePage_Idle Predicate: doingStore && (stateRequest == 2'd0) && (stateStore == 2'd0) Blocking rules: (none) Rule: loadPage_Data Predicate: doingLoad && (stateLoad == 2'd1) Blocking rules: (none) Rule: loadPage_Requesting Predicate: doingLoad && (stateRequest == 2'd1) && (stateLoad == 2'd0) Blocking rules: (none) Rule: loadPage_Idle Predicate: doingLoad && (stateRequest == 2'd0) && (stateLoad == 2'd0) Blocking rules: storePage_Idle Rule: startPageStore Predicate: plbMasterCommandInfifo.i_notEmpty && (! (plbMasterCommandInfifo.first[31:30] == 2'd0)) && (! (plbMasterCommandInfifo.first[31:30] == 2'd1)) && (! doingStore) Blocking rules: (none) Rule: startPageLoad Predicate: plbMasterCommandInfifo.i_notEmpty && (plbMasterCommandInfifo.first[31:30] == 2'd1) && (! doingLoad) Blocking rules: (none) Logical execution order: plbMasterWires_plbIN, plbMasterWires_mWrDBus, plbMasterWires_mWrBurst, plbMasterWires_mType, plbMasterWires_mSize, plbMasterWires_mRequest, plbMasterWires_mRdBurst, plbMasterWires_mPriority, plbMasterWires_mOrdered, plbMasterWires_mMSize, plbMasterWires_mLockErr, plbMasterWires_mGuarded, plbMasterWires_mCompress, plbMasterWires_mBusLock, plbMasterWires_mAbort, plbMasterWires_mRNW, plbMasterWires_mABus, plbMasterWires_mBE, plbMasterCommandInput_put, wordOutput_get, wordInput_put, wordToRecord, writeStoreData, storePage_WaitForBusy, storePage_Data, storePage_Requesting, storePage_Idle, loadPage_Data, loadPage_Requesting, loadPage_Idle, startPageStore, startPageLoad =========================================== 1.1 cryptosorter/memocodeDesignContest2008/xup/PLBMaster/mkPLBMasterTester.sched http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/xup/PLBMaster/mkPLBMasterTester.sched?rev=1.1&content-type=text/x-cvsweb-markup Index: mkPLBMasterTester.sched =================================================================== === Generated schedule for mkPLBMasterTester === Method schedule --------------- Method: plbMasterWires_mABus Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN, bramInitiatorWires_bramCLK, bramInitiatorWires_bramRST, bramInitiatorWires_bramAddr, bramInitiatorWires_bramDout, bramInitiatorWires_bramDin, bramInitiatorWires_bramWEN, bramInitiatorWires_bramEN Method: plbMasterWires_mBE Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN, bramInitiatorWires_bramCLK, bramInitiatorWires_bramRST, bramInitiatorWires_bramAddr, bramInitiatorWires_bramDout, bramInitiatorWires_bramDin, bramInitiatorWires_bramWEN, bramInitiatorWires_bramEN Method: plbMasterWires_mRNW Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN, bramInitiatorWires_bramCLK, bramInitiatorWires_bramRST, bramInitiatorWires_bramAddr, bramInitiatorWires_bramDout, bramInitiatorWires_bramDin, bramInitiatorWires_bramWEN, bramInitiatorWires_bramEN Method: plbMasterWires_mAbort Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN, bramInitiatorWires_bramCLK, bramInitiatorWires_bramRST, bramInitiatorWires_bramAddr, bramInitiatorWires_bramDout, bramInitiatorWires_bramDin, bramInitiatorWires_bramWEN, bramInitiatorWires_bramEN Method: plbMasterWires_mBusLock Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN, bramInitiatorWires_bramCLK, bramInitiatorWires_bramRST, bramInitiatorWires_bramAddr, bramInitiatorWires_bramDout, bramInitiatorWires_bramDin, bramInitiatorWires_bramWEN, bramInitiatorWires_bramEN Method: plbMasterWires_mCompress Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN, bramInitiatorWires_bramCLK, bramInitiatorWires_bramRST, bramInitiatorWires_bramAddr, bramInitiatorWires_bramDout, bramInitiatorWires_bramDin, bramInitiatorWires_bramWEN, bramInitiatorWires_bramEN Method: plbMasterWires_mGuarded Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN, bramInitiatorWires_bramCLK, bramInitiatorWires_bramRST, bramInitiatorWires_bramAddr, bramInitiatorWires_bramDout, bramInitiatorWires_bramDin, bramInitiatorWires_bramWEN, bramInitiatorWires_bramEN Method: plbMasterWires_mLockErr Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN, bramInitiatorWires_bramCLK, bramInitiatorWires_bramRST, bramInitiatorWires_bramAddr, bramInitiatorWires_bramDout, bramInitiatorWires_bramDin, bramInitiatorWires_bramWEN, bramInitiatorWires_bramEN Method: plbMasterWires_mMSize Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN, bramInitiatorWires_bramCLK, bramInitiatorWires_bramRST, bramInitiatorWires_bramAddr, bramInitiatorWires_bramDout, bramInitiatorWires_bramDin, bramInitiatorWires_bramWEN, bramInitiatorWires_bramEN Method: plbMasterWires_mOrdered Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN, bramInitiatorWires_bramCLK, bramInitiatorWires_bramRST, bramInitiatorWires_bramAddr, bramInitiatorWires_bramDout, bramInitiatorWires_bramDin, bramInitiatorWires_bramWEN, bramInitiatorWires_bramEN Method: plbMasterWires_mPriority Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMasterWires_mMSize, plbMasterWires_mOrdered, plbMasterWires_mPriority, plbMasterWires_mRdBurst, plbMasterWires_mRequest, plbMasterWires_mSize, plbMasterWires_mType, plbMasterWires_mWrBurst, plbMasterWires_mWrDBus, plbMasterWires_plbIN, bramInitiatorWires_bramCLK, bramInitiatorWires_bramRST, bramInitiatorWires_bramAddr, bramInitiatorWires_bramDout, bramInitiatorWires_bramDin, bramInitiatorWires_bramWEN, bramInitiatorWires_bramEN Method: plbMasterWires_mRdBurst Ready signal: True Conflict-free: plbMasterWires_mABus, plbMasterWires_mBE, plbMasterWires_mRNW, plbMasterWires_mAbort, plbMasterWires_mBusLock, plbMasterWires_mCompress, plbMasterWires_mGuarded, plbMasterWires_mLockErr, plbMa