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From: cvs at opencores.org<cvs@o...>
Date: Mon Jun 30 18:02:01 CEST 2008
Subject: [cvs-checkins] MODIFIED: cryptosorter ...
Date: 00/08/06 30:18:02

Added: cryptosorter/memocodeDesignContest2008/aesCore/verilog/sim/rtl_sim/bin
Makefile aes_sbox.dat
Log:
Initial checkin with actual source




Revision Changes Path
1.1 cryptosorter/memocodeDesignContest2008/aesCore/verilog/sim/rtl_sim/bin/Makefile

http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/aesCore/verilog/sim/rtl_sim/bin/Makefile?rev=1.1&content-type=text/x-cvsweb-markup

Index: Makefile
===================================================================
all: sim
SHELL = /bin/sh
MS="-s"

##########################################################################
#
# DUT Sources
#
##########################################################################
DUT_SRC_DIR=../../../rtl/verilog
_TARGETS_= $(DUT_SRC_DIR)/aes_sbox.v \
$(DUT_SRC_DIR)/aes_key_expand_128.v \
$(DUT_SRC_DIR)/aes_rcon.v \
$(DUT_SRC_DIR)/aes_cipher_top.v \
$(DUT_SRC_DIR)/aes_inv_sbox.v \
$(DUT_SRC_DIR)/aes_inv_cipher_top.v





##########################################################################
#
# Test Bench Sources
#
##########################################################################
TB_SRC_DIR=../../../bench/verilog
_TB_= $(TB_SRC_DIR)/test_bench_top.v
_TBSB_= $(TB_SRC_DIR)/test_bench_sbox_top.v

##########################################################################
#
# Misc Variables
#
##########################################################################

INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
LOGF=-l .nclog
UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
GATE_NETLIST = ../../../syn/out/aes_cipher_top.v

##########################################################################
#
# Make Targets
#
##########################################################################
ss:
signalscan -do waves/waves.do -waves waves/waves.trn &

simw:
@$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"

sim:
ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_) \
$(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus \
+ncuid+`hostname`

ivl:
iverilog -D RUDIS_TB $(_TARGETS_) $(_TB_) \
-I ./$(DUT_SRC_DIR)/ -I ./$(TB_SRC_DIR)/ \
$(WAVES) $(ACCESS) -s test

ivl_sb:
iverilog -D RUDIS_TB $(_TARGETS_) $(_TBSB_) \
-I ./$(DUT_SRC_DIR)/ -I ./$(TB_SRC_DIR)/ \
$(WAVES) $(ACCESS) -s test

gatew:
@$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"

gate:
ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB) \
$(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS) \
$(LOGF) +ncstatus +ncuid+`hostname`

hal:
@echo ""
@echo "----- Running HAL ... ----------"
@hal +incdir+$(DUT_SRC_DIR) -NOP -NOS \
-nocheck STYVAL:USEPRT:NOBLKN:DLNBLK \
$(_TARGETS_)
@echo "----- DONE ... ----------"

clean:
rm -rf ./waves/*.dsn ./waves/*.trn \
ncwork/.inc* ncwork/inc* \ ./verilog.* .nclog hal.log INCA_libs a.out dump.vcd *~ ########################################################################## 1.1 cryptosorter/memocodeDesignContest2008/aesCore/verilog/sim/rtl_sim/bin/aes_sbox.dat http://www.opencores.org/cvsweb.shtml/cryptosorter/memocodeDesignContest2008/aesCore/verilog/sim/rtl_sim/bin/aes_sbox.dat?rev=1.1&content-type=text/x-cvsweb-markup Index: aes_sbox.dat =================================================================== 63 7c 77 7b f2 6b 6f c5 30 01 67 2b fe d7 ab 76 ca 82 c9 7d fa 59 47 f0 ad d4 a2 af 9c a4 72 c0 b7 fd 93 26 36 3f f7 cc 34 a5 e5 f1 71 d8 31 15 04 c7 23 c3 18 96 05 9a 07 12 80 e2 eb 27 b2 75 09 83 2c 1a 1b 6e 5a a0 52 3b d6 b3 29 e3 2f 84 53 d1 00 ed 20 fc b1 5b 6a cb be 39 4a 4c 58 cf d0 ef aa fb 43 4d 33 85 45 f9 02 7f 50 3c 9f a8 51 a3 40 8f 92 9d 38 f5 bc b6 da 21 10 ff f3 d2 cd 0c 13 ec 5f 97 44 17 c4 a7 7e 3d 64 5d 19 73 60 81 4f dc 22 2a 90 88 46 ee b8 14 de 5e 0b db e0 32 3a 0a 49 06 24 5c c2 d3 ac 62 91 95 e4 79 e7 c8 37 6d 8d d5 4e a9 6c 56 f4 ea 65 7a ae 08 ba 78 25 2e 1c a6 b4 c6 e8 dd 74 1f 4b bd 8b 8a 70 3e b5 66 48 03 f6 0e 61 35 57 b9 86 c1 1d 9e e1 f8 98 11 69 d9 8e 94 9b 1e 87 e9 ce 55 28 df 8c a1 89 0d bf e6 42 68 41 99 2d 0f b0 54 bb 16