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From: cvs at opencores.org<cvs@o...>
Date: Fri May 30 16:02:59 CEST 2008
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/08/05 30:16:02

Modified: aemb/sim/verilog edk62.v
Log:
added random seed




Revision Changes Path
1.4 aemb/sim/verilog/edk62.v

http://www.opencores.org/cvsweb.shtml/aemb/sim/verilog/edk62.v.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: edk62.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/sim/verilog/edk62.v,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- edk62.v 1 May 2008 08:33:20 -0000 1.3
+++ edk62.v 30 May 2008 14:02:59 -0000 1.4
@@ -1,4 +1,4 @@
-/* $Id: edk62.v,v 1.3 2008/05/01 08:33:20 sybreon Exp $
+/* $Id: edk62.v,v 1.4 2008/05/30 14:02:59 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@a...>
@@ -25,6 +25,8 @@

*/

+`include "random.v"
+
module edk62();
localparam AEMB_DWB = 18;
localparam AEMB_XWB = 5;
@@ -57,7 +59,7 @@
$dumpvars (1,uut);
`endif

- sys_clk_i = 0;
+ sys_clk_i = $random(`randseed);
sys_rst_i = 1;
sys_ena_i = 1;
sys_int_i = 1;
@@ -260,6 +262,9 @@
endmodule // edk62

// $Log: edk62.v,v $
+// Revision 1.4 2008/05/30 14:02:59 sybreon
+// added random seed
+//
// Revision 1.3 2008/05/01 08:33:20 sybreon
// Added interrupt capability.
//