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From: cvs at opencores.org<cvs@o...>
Date: Tue May 27 21:01:58 CEST 2008
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/08/05 27:21:01

Modified: aemb/sim iversim
Log:
Modified script to use verilog pre-processing.

Changed /bin/bash to /bin/sh as suggested by "Wojciech A. Koszek" <wkoszek@f...> for FreeBSD compatibility.


Revision Changes Path
1.8 aemb/sim/iversim

http://www.opencores.org/cvsweb.shtml/aemb/sim/iversim.diff?r1=1.7&r2=1.8

(In the diff below, changes in quantity of whitespace are not shown.)

Index: iversim
===================================================================
RCS file: /cvsroot/sybreon/aemb/sim/iversim,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- iversim 1 May 2008 08:33:52 -0000 1.7
+++ iversim 27 May 2008 19:01:58 -0000 1.8
@@ -1,30 +1,47 @@
-#!/bin/bash
-# $Id: iversim,v 1.7 2008/05/01 08:33:52 sybreon Exp $
+#!/bin/sh
+# $Id: iversim,v 1.8 2008/05/27 19:01:58 sybreon Exp $
+
+HERE=$(dirname $0)
+RANDOM=$(date +%s)
+SIM="isim"
+IVERLIB="-y$HERE/../rtl/verilog"
+
+# seed random number
+echo "\`define randseed $RANDOM" > random.v
+
+# pre-processor
+iverilog $IVERLIB -tnull -M$SIM.ls $@ && \
+sed 1d < $SIM.ls > $SIM.fs && \
+iverilog -c$SIM.fs -E -tnull -o $SIM.v $@ && \
+rm $SIM.ls $SIM.fs && \
+rm random.v && \
+
+# simulation
+if [ -e "$SIM.v" ]; then
+ iverilog -tvvp -o $SIM.vvp $SIM.v && \
+ vvp -l iverilog.log $SIM.vvp && \
+ rm $SIM.vvp
+fi
+
+# recompress
+if [ -e "dump.vcd" ]; then
+ vcd2lxt dump.vcd dump.lxt -stats && \
+ rm dump.vcd
+fi
+
+echo "DONE"
+
# $Log: iversim,v $
-# Revision 1.7 2008/05/01 08:33:52 sybreon
-# Minor cosmetic changes.
-#
-# Revision 1.6 2008/04/27 16:28:53 sybreon
-# Added VCD2LXT functions.
-#
-# Revision 1.5 2007/12/11 00:44:30 sybreon
-# Modified for AEMB2
+# Revision 1.8 2008/05/27 19:01:58 sybreon
+# Modified script to use verilog pre-processing.
+# Changed /bin/bash to /bin/sh as suggested by "Wojciech A. Koszek" <wkoszek@f...> for FreeBSD compatibility.
#
-# Revision 1.4 2007/11/30 17:08:30 sybreon
-# Moved simulation kernel into code.
+# Revision 1.4 2008/05/13 20:05:13 ssnt2
+# *** empty log message ***
#
-# Revision 1.3 2007/11/09 20:50:51 sybreon
-# Added log output to iverilog.log
+# Revision 1.3 2008/05/09 16:20:03 ssnt2
+# added vcd2lxt recompressor.
#
-# Revision 1.2 2007/11/05 10:59:31 sybreon
-# Added random seed for simulation.
+# Revision 1.2 2008/05/09 16:13:59 ssnt2
+# added pre-processor and cleaned up code.
#
-# Revision 1.1 2007/03/09 17:41:55 sybreon
-# initial import
-#
-RANDOM=$(date +%s)
-echo "parameter randseed = $RANDOM;" > random.v
-iverilog $@ -y../rtl/verilog/ -y./verilog/ && echo "VER=$?"
-vvp -l iverilog.log a.out && echo "VVP=$?"
-vcd2lxt2 dump.vcd dump.lxt && echo "LXT=$?"
-rm *.vcd && rm a.out