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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat May 24 17:42:59 CEST 2008
Subject: [cvs-checkins] MODIFIED: z80soc ...
Date: 00/08/05 24:17:42 Modified: z80soc/DE1 z80soc.qsf
Added: z80soc/DE1 z80soc.sof
Log:
Version 0.6
Revision Changes Path
1.2 z80soc/DE1/z80soc.qsf
http://www.opencores.org/cvsweb.shtml/z80soc/DE1/z80soc.qsf.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: z80soc.qsf
===================================================================
RCS file: /cvsroot/rrred/z80soc/DE1/z80soc.qsf,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- z80soc.qsf 4 May 2008 20:48:51 -0000 1.1
+++ z80soc.qsf 24 May 2008 15:42:59 -0000 1.2
@@ -482,10 +482,16 @@
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
+set_global_assignment -name VHDL_FILE rtl/VHDL/VIDEO.vhd
+set_global_assignment -name VHDL_FILE rtl/VHDL/t80/T80se.vhd
set_global_assignment -name VHDL_FILE rtl/VHDL/clk_div.vhd
set_global_assignment -name VHDL_FILE rtl/VHDL/PS2/KEYBOARD.VHD
set_global_assignment -name VHDL_FILE rtl/VHDL/PS2/ps2bkd.vhd
-set_global_assignment -name VHDL_FILE rtl/VHDL/VIDEO_80X40.vhd
set_global_assignment -name VHDL_FILE rtl/vhdl/vga_sync.vhd
set_global_assignment -name VHDL_FILE rtl/vhdl/CHAR_ROM.VHD
set_global_assignment -name VHDL_FILE rtl/vhdl/video_PLL.vhd
@@ -494,14 +500,9 @@
set_global_assignment -name VHDL_FILE rtl/vhdl/rom.vhd
set_global_assignment -name VHDL_FILE rtl/vhdl/top_de1.vhd
set_global_assignment -name VHDL_FILE rtl/vhdl/decoder_7seg.vhd
-set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80s.vhd
set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80.vhd
set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_Reg.vhd
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
\ No newline at end of file
+set_parameter -name CYCLONEII_SAFE_WRITE "\"RESTRUCTURE\"" -to "vram8k:vram8k_inst"
\ No newline at end of file
1.1 z80soc/DE1/z80soc.sof
http://www.opencores.org/cvsweb.shtml/z80soc/DE1/z80soc.sof?rev=1.1&content-type=text/x-cvsweb-markup
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