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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat May 24 17:39:15 CEST 2008
Subject: [cvs-checkins] MODIFIED: z80soc ...
Date: 00/08/05 24:17:39 Modified: z80soc/DE1/rtl/VHDL/t80 T80.vhd T80_ALU.vhd T80_MCode.vhd
T80_Pack.vhd T80_Reg.vhd T80_RegX.vhd T80s.vhd
T80se.vhd
Added: z80soc/DE1/rtl/VHDL/t80 T80sed.vhd
Log:
Version 0.6
Revision Changes Path
1.2 z80soc/DE1/rtl/VHDL/t80/T80.vhd
http://www.opencores.org/cvsweb.shtml/z80soc/DE1/rtl/VHDL/t80/T80.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: T80.vhd
===================================================================
RCS file: /cvsroot/rrred/z80soc/DE1/rtl/VHDL/t80/T80.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- T80.vhd 4 May 2008 20:53:58 -0000 1.1
+++ T80.vhd 24 May 2008 15:39:14 -0000 1.2
@@ -1,3 +1,13 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
--
-- Z80 compatible microprocessor core
--
@@ -128,6 +138,7 @@
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
+
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
@@ -643,7 +654,7 @@
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
- if TState = 1 and Auto_Wait_t1 = '0' then
+ if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
@@ -674,7 +685,7 @@
F(Flag_P) <= IncDecZ;
end if;
- if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
+ if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
@@ -770,7 +781,7 @@
begin
RegWEH <= '0';
RegWEL <= '0';
- if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
+ if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
@@ -976,11 +987,7 @@
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
- if T_Res = '1' then
- Auto_Wait_t1 <= '0';
- else
- Auto_Wait_t1 <= Auto_Wait or IORQ_i;
- end if;
+ Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
@@ -1047,8 +1054,8 @@
end if;
end if;
else
- if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
- (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
+ if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
TState <= TState + 1;
end if;
end if;
1.2 z80soc/DE1/rtl/VHDL/t80/T80_ALU.vhd
http://www.opencores.org/cvsweb.shtml/z80soc/DE1/rtl/VHDL/t80/T80_ALU.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: T80_ALU.vhd
===================================================================
RCS file: /cvsroot/rrred/z80soc/DE1/rtl/VHDL/t80/T80_ALU.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- T80_ALU.vhd 4 May 2008 20:54:08 -0000 1.1
+++ T80_ALU.vhd 24 May 2008 15:39:14 -0000 1.2
@@ -1,3 +1,13 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
--
-- Z80 compatible microprocessor core
--
@@ -93,6 +103,7 @@
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
+
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
@@ -101,6 +112,7 @@
else
B_i := unsigned(B);
end if;
+
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
@@ -131,7 +143,16 @@
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+
+ -- bug fix - parity flag is just parity for 8080, also overflow for Z80
+ process (Carry_v, Carry7_v, Q_v)
+ begin
+ if(Mode=2) then
+ OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
+ Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
+ end if;
+ end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
@@ -347,5 +368,4 @@
end case;
Q <= Q_t;
end process;
-
end;
1.2 z80soc/DE1/rtl/VHDL/t80/T80_MCode.vhd
http://www.opencores.org/cvsweb.shtml/z80soc/DE1/rtl/VHDL/t80/T80_MCode.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: T80_MCode.vhd
===================================================================
RCS file: /cvsroot/rrred/z80soc/DE1/rtl/VHDL/t80/T80_MCode.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- T80_MCode.vhd 4 May 2008 20:54:22 -0000 1.1
+++ T80_MCode.vhd 24 May 2008 15:39:14 -0000 1.2
@@ -1,3 +1,12 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
--
-- Z80 compatible microprocessor core
--
@@ -57,6 +66,8 @@
-- 0238b: Fixed instruction timing for POP and DJNZ
--
-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
+
+-- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
--
-- 0242 : Fixed I/O instruction timing, cleanup
--
@@ -64,6 +75,7 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
+use work.T80_Pack.all;
entity T80_MCode is
generic(
@@ -143,13 +155,6 @@
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
--- constant aNone : std_logic_vector(2 downto 0) := "000";
--- constant aXY : std_logic_vector(2 downto 0) := "001";
--- constant aIOA : std_logic_vector(2 downto 0) := "010";
--- constant aSP : std_logic_vector(2 downto 0) := "011";
--- constant aBC : std_logic_vector(2 downto 0) := "100";
--- constant aDE : std_logic_vector(2 downto 0) := "101";
--- constant aZI : std_logic_vector(2 downto 0) := "110";
function is_cc_true(
F : std_logic_vector(7 downto 0);
@@ -1404,12 +1409,12 @@
-- BIT b,(HL)
MCycles <= "010";
case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
+ when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1001";
TStates <= "100";
- when others =>
+ when others => null;
end case;
when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
|"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
@@ -1429,7 +1434,7 @@
-- SET b,(HL)
MCycles <= "011";
case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
+ when 1 | 7=>
Set_Addr_To <= aXY;
when 2 =>
ALU_Op <= "1010";
@@ -1439,7 +1444,7 @@
TStates <= "100";
when 3 =>
Write <= '1';
- when others =>
+ when others => null;
end case;
when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
|"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
@@ -1469,7 +1474,7 @@
TStates <= "100";
when 3 =>
Write <= '1';
- when others =>
+ when others => null;
end case;
end case;
@@ -1822,6 +1827,7 @@
end case;
when "10100010" | "10101010" | "10110010" | "10111010" =>
-- INI, IND, INIR, INDR
+ -- note B is decremented AFTER being put on the bus
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
@@ -1837,9 +1843,11 @@
Set_Addr_To <= aXY;
when 3 =>
if IR(3) = '0' then
- IncDec_16 <= "0010";
+ --IncDec_16 <= "0010";
+ IncDec_16 <= "0110";
else
- IncDec_16 <= "1010";
+ --IncDec_16 <= "1010";
+ IncDec_16 <= "1110";
end if;
TStates <= "100";
Write <= '1';
@@ -1851,6 +1859,8 @@
end case;
when "10100011" | "10101011" | "10110011" | "10111011" =>
-- OUTI, OUTD, OTIR, OTDR
+ -- note B is decremented BEFORE being put on the bus.
+ -- mikej fix for hl inc
MCycles <= "100";
case to_integer(unsigned(MCycle)) is
when 1 =>
@@ -1866,9 +1876,9 @@
Set_Addr_To <= aBC;
when 3 =>
if IR(3) = '0' then
- IncDec_16 <= "0010";
+ IncDec_16 <= "0110"; -- mikej
else
- IncDec_16 <= "1010";
+ IncDec_16 <= "1110"; -- mikej
end if;
IORQ <= '1';
Write <= '1';
1.2 z80soc/DE1/rtl/VHDL/t80/T80_Pack.vhd
http://www.opencores.org/cvsweb.shtml/z80soc/DE1/rtl/VHDL/t80/T80_Pack.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: T80_Pack.vhd
===================================================================
RCS file: /cvsroot/rrred/z80soc/DE1/rtl/VHDL/t80/T80_Pack.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- T80_Pack.vhd 4 May 2008 20:54:23 -0000 1.1
+++ T80_Pack.vhd 24 May 2008 15:39:14 -0000 1.2
@@ -1,3 +1,12 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
--
-- Z80 compatible microprocessor core
--
1.2 z80soc/DE1/rtl/VHDL/t80/T80_Reg.vhd
http://www.opencores.org/cvsweb.shtml/z80soc/DE1/rtl/VHDL/t80/T80_Reg.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: T80_Reg.vhd
===================================================================
RCS file: /cvsroot/rrred/z80soc/DE1/rtl/VHDL/t80/T80_Reg.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
1.2 z80soc/DE1/rtl/VHDL/t80/T80_RegX.vhd
http://www.opencores.org/cvsweb.shtml/z80soc/DE1/rtl/VHDL/t80/T80_RegX.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: T80_RegX.vhd
===================================================================
RCS file: /cvsroot/rrred/z80soc/DE1/rtl/VHDL/t80/T80_RegX.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- T80_RegX.vhd 4 May 2008 20:54:25 -0000 1.1
+++ T80_RegX.vhd 24 May 2008 15:39:14 -0000 1.2
@@ -1,3 +1,12 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
--
-- T80 Registers for Xilinx Select RAM
--
1.2 z80soc/DE1/rtl/VHDL/t80/T80s.vhd
http://www.opencores.org/cvsweb.shtml/z80soc/DE1/rtl/VHDL/t80/T80s.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: T80s.vhd
===================================================================
RCS file: /cvsroot/rrred/z80soc/DE1/rtl/VHDL/t80/T80s.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
1.2 z80soc/DE1/rtl/VHDL/t80/T80se.vhd
http://www.opencores.org/cvsweb.shtml/z80soc/DE1/rtl/VHDL/t80/T80se.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: T80se.vhd
===================================================================
RCS file: /cvsroot/rrred/z80soc/DE1/rtl/VHDL/t80/T80se.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- T80se.vhd 4 May 2008 20:54:05 -0000 1.1
+++ T80se.vhd 24 May 2008 15:39:14 -0000 1.2
@@ -1,9 +1,18 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
--- Version : 0242
+-- Version : 0240
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@o...)
--
@@ -58,7 +67,6 @@
--
-- 0242 : Updated for T80 interface change
--
-
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -67,8 +75,8 @@
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
- IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
+ T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
+ IOWait : integer := 0 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
1.1 z80soc/DE1/rtl/VHDL/t80/T80sed.vhd
http://www.opencores.org/cvsweb.shtml/z80soc/DE1/rtl/VHDL/t80/T80sed.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: T80sed.vhd
===================================================================
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0238
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@o...)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80sed is
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80sed;
architecture rtl of T80sed is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => 0,
IOWait => 1)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if ((TState = "001") or (TState = "010")) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;
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