LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cvs-checkins > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: cvs at opencores.org<cvs@o...>
    Date: Tue Apr 29 23:17:16 CEST 2008
    Subject: [cvs-checkins] MODIFIED: t48 ...
    Top
    Date: 00/08/04 29:23:17

    Modified: t48/sim/rtl_sim Makefile.hier Makefile.ghdl
    Log:
    update to new mnemonic decoder










    Revision Changes Path
    1.16 t48/sim/rtl_sim/Makefile.hier

    http://www.opencores.org/cvsweb.shtml/t48/sim/rtl_sim/Makefile.hier.diff?r1=1.15&r2=1.16

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: Makefile.hier
    ===================================================================
    RCS file: /cvsroot/arniml/t48/sim/rtl_sim/Makefile.hier,v
    retrieving revision 1.15
    retrieving revision 1.16
    diff -u -b -r1.15 -r1.16
    --- Makefile.hier 14 Jul 2006 01:08:45 -0000 1.15
    +++ Makefile.hier 29 Apr 2008 21:17:16 -0000 1.16
    @@ -110,11 +110,11 @@
    $(decoder_pack)
    $(ANALYZE) $<

    -$(decoder_pack) : $(RTL_DIR)/decoder_pack-p.vhd
    +$(decoder_pack) : $(RTL_DIR)/decoder_pack-p.vhd \
    + $(t48_pack)
    $(ANALYZE) $<

    $(decoder_rtl_c0) : $(RTL_DIR)/decoder-c.vhd \
    - $(opc_decoder_rtl_c0) \
    $(int_rtl_c0) \
    $(decoder)
    $(ANALYZE) $<
    @@ -139,30 +139,6 @@
    $(int)
    $(ANALYZE) $<

    -$(opc_decoder) : $(RTL_DIR)/opc_decoder.vhd \
    - $(decoder_pack) \
    - $(t48_pack) \
    - $(pmem_ctrl_pack) \
    - $(dmem_ctrl_pack) \
    - $(cond_branch_pack) \
    - $(alu_pack) \
    - $(t48_comp_pack)
    - $(ANALYZE) $<
    -
    -$(opc_decoder_rtl_c0) : $(RTL_DIR)/opc_decoder-c.vhd \
    - $(opc_table_rtl_c0) \
    - $(opc_decoder)
    - $(ANALYZE) $<
    -
    -$(opc_table) : $(RTL_DIR)/opc_table.vhd \
    - $(decoder_pack) \
    - $(t48_pack)
    - $(ANALYZE) $<
    -
    -$(opc_table_rtl_c0) : $(RTL_DIR)/opc_table-c.vhd \
    - $(opc_table)
    - $(ANALYZE) $<
    -
    $(p1) : $(RTL_DIR)/p1.vhd \
    $(t48_pack)
    $(ANALYZE) $<



    1.15 t48/sim/rtl_sim/Makefile.ghdl

    http://www.opencores.org/cvsweb.shtml/t48/sim/rtl_sim/Makefile.ghdl.diff?r1=1.14&r2=1.15

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: Makefile.ghdl
    ===================================================================
    RCS file: /cvsroot/arniml/t48/sim/rtl_sim/Makefile.ghdl,v
    retrieving revision 1.14
    retrieving revision 1.15
    diff -u -b -r1.14 -r1.15
    --- Makefile.ghdl 14 Jul 2006 01:08:45 -0000 1.14
    +++ Makefile.ghdl 29 Apr 2008 21:17:16 -0000 1.15
    @@ -91,10 +91,6 @@
    p1 = $(LIB_WORK)/p1.o
    timer_rtl_c0 = $(LIB_WORK)/timer-c.o
    timer = $(LIB_WORK)/timer.o
    -opc_table_rtl_c0 = $(LIB_WORK)/opc_table-c.o
    -opc_table = $(LIB_WORK)/opc_table.o
    -opc_decoder_rtl_c0 = $(LIB_WORK)/opc_decoder-c.o
    -opc_decoder = $(LIB_WORK)/opc_decoder.o
    int_rtl_c0 = $(LIB_WORK)/int-c.o
    int = $(LIB_WORK)/int.o
    dmem_ctrl_rtl_c0 = $(LIB_WORK)/dmem_ctrl-c.o

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.