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From: cvs at opencores.org<cvs@o...>
Date: Mon Apr 28 00:15:43 CEST 2008
Subject: [cvs-checkins] MODIFIED: t400 ...
Date: 00/08/04 28:00:15

Modified: t400 README
Log:
added syn directory




Revision Changes Path
1.6 t400/README

http://www.opencores.org/cvsweb.shtml/t400/README.diff?r1=1.5&r2=1.6

(In the diff below, changes in quantity of whitespace are not shown.)

Index: README
===================================================================
RCS file: /cvsroot/arniml/t400/README,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -b -r1.5 -r1.6
--- README 12 Jun 2006 00:09:56 -0000 1.5
+++ README 27 Apr 2008 22:15:43 -0000 1.6
@@ -1,7 +1,7 @@

README for the T400 uController project
=======================================
-Version: $Date: 2006/06/12 00:09:56 $
+Version: $Date: 2008/04/27 22:15:43 $


Introduction
@@ -93,6 +93,12 @@
| |
| \-- rtl_sim : Directory for running simulations.
|
+ +-- syn
+ | |
+ | +-- ep1c12 : Synthesis for Altera Cyclone.
+ | |
+ | \-- xc3s1000 : Synthesis for Xilinx Spartan3.
+ |
\-- sw : General purpose scripts and files.
|
\-- verif : The verification suite.
@@ -183,7 +189,7 @@
----------------------------

All testbenches listed above load the internal ROM of the controller from a
-file in hex-format. Its existance is mandatory as it is referenced in the
+file in hex-format. Its existance is mandatory since it is referenced in the
VHDL code of the ROM model lpm_rom.vhd. In case it is missing, the
simulation will stop immediately after elaborating the design.