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From: cvs at opencores.org<cvs@o...>
Date: Mon Apr 28 00:13:16 CEST 2008
Subject: [cvs-checkins] MODIFIED: t400 ...
Date: 00/08/04 28:00:13

Modified: t400/rtl/tech/generic generic_ram_ena.vhd generic_ram.vhd
Log:
convert to read-before-write style




Revision Changes Path
1.3 t400/rtl/tech/generic/generic_ram_ena.vhd

http://www.opencores.org/cvsweb.shtml/t400/rtl/tech/generic/generic_ram_ena.vhd.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: generic_ram_ena.vhd
===================================================================
RCS file: /cvsroot/arniml/t400/rtl/tech/generic/generic_ram_ena.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- generic_ram_ena.vhd 17 Jun 2006 14:20:59 -0000 1.2
+++ generic_ram_ena.vhd 27 Apr 2008 22:13:15 -0000 1.3
@@ -2,7 +2,7 @@
--
-- Parametrizable, generic RAM with enable.
--
--- $Id: generic_ram_ena.vhd,v 1.2 2006/06/17 14:20:59 arniml Exp $
+-- $Id: generic_ram_ena.vhd,v 1.3 2008/04/27 22:13:15 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@o...)
--
@@ -76,7 +76,6 @@
:= (others => (others => '0'))
-- pragma translate_on
;
- signal a_q : std_logic_vector(a_i'range);

begin

@@ -89,12 +88,10 @@
mem_q(to_integer(unsigned(a_i))) <= d_i;
end if;

- a_q <= a_i;
+ d_o <= mem_q(to_integer(unsigned(a_i)));
end if;

end if;
end process mem;

- d_o <= mem_q(to_integer(unsigned(a_q)));
-
end rtl;



1.3 t400/rtl/tech/generic/generic_ram.vhd

http://www.opencores.org/cvsweb.shtml/t400/rtl/tech/generic/generic_ram.vhd.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: generic_ram.vhd
===================================================================
RCS file: /cvsroot/arniml/t400/rtl/tech/generic/generic_ram.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- generic_ram.vhd 17 Jun 2006 14:20:59 -0000 1.2
+++ generic_ram.vhd 27 Apr 2008 22:13:15 -0000 1.3
@@ -2,7 +2,7 @@
--
-- Parametrizable, generic RAM.
--
--- $Id: generic_ram.vhd,v 1.2 2006/06/17 14:20:59 arniml Exp $
+-- $Id: generic_ram.vhd,v 1.3 2008/04/27 22:13:15 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@o...)
--
@@ -75,7 +75,6 @@
:= (others => (others => '0'))
-- pragma translate_on
;
- signal a_q : std_logic_vector(a_i'range);

begin

@@ -87,11 +86,9 @@
mem_q(to_integer(unsigned(a_i))) <= d_i;
end if;

- a_q <= a_i;
+ d_o <= mem_q(to_integer(unsigned(a_i)));
end if;

end process mem;

- d_o <= mem_q(to_integer(unsigned(a_q)));
-
end rtl;