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Message
From: cvs at opencores.org<cvs@o...>
Date: Sun Apr 27 18:41:55 CEST 2008
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/08/04 27:18:41 Modified: aemb/rtl/verilog aeMB2_dwbif.v
Log:
Disconnect from pipeline.
Revision Changes Path
1.7 aemb/rtl/verilog/aeMB2_dwbif.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB2_dwbif.v.diff?r1=1.6&r2=1.7
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB2_dwbif.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB2_dwbif.v,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- aeMB2_dwbif.v 26 Apr 2008 17:57:43 -0000 1.6
+++ aeMB2_dwbif.v 27 Apr 2008 16:41:55 -0000 1.7
@@ -1,4 +1,4 @@
-/* $Id: aeMB2_dwbif.v,v 1.6 2008/04/26 17:57:43 sybreon Exp $
+/* $Id: aeMB2_dwbif.v,v 1.7 2008/04/27 16:41:55 sybreon Exp $
**
** AEMB2 EDK 6.2 COMPATIBLE CORE
** Copyright (C) 2004-2008 Shawn Tan <shawn.tan@a...>
@@ -129,7 +129,10 @@
dwb_wre_o <= #1 opc_of[2]; // SXX
- dwb_mx <= #1 (dwb_ack_i) ? dwb_dat_i : dwb_lat; // Latch input
+ dwb_mx <= #1
+ (dwb_ack_i) ?
+ dwb_dat_i : // stalled from RAM
+ dwb_lat; // latch earlier data
case (wSEL) // Latch output
// 32'bit
@@ -171,7 +174,7 @@
dwb_stb_o <= 1'h0;
// End of automatics
//end else if (dwb_fb) begin
- end else if (dena) begin
+ end else if (dwb_fb) begin
dwb_stb_o <= #1
(dena) ? &opc_of[5:4] : // LXX/SSS
(dwb_stb_o & !dwb_ack_i); // LXX/SSS
@@ -186,6 +189,9 @@
/*
$Log: aeMB2_dwbif.v,v $
+ Revision 1.7 2008/04/27 16:41:55 sybreon
+ Disconnect from pipeline.
+
Revision 1.6 2008/04/26 17:57:43 sybreon
Minor performance improvements.
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