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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat Apr 26 21:31:35 CEST 2008
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/08/04 26:21:31 Modified: aemb/sw/cc/aemb core.hh heap.hh hook.hh msr.hh stack.hh
stdio.hh thread.hh
Log:
Made headers C compatible.
Revision Changes Path
1.2 aemb/sw/cc/aemb/core.hh
http://www.opencores.org/cvsweb.shtml/aemb/sw/cc/aemb/core.hh.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: core.hh
===================================================================
RCS file: /cvsroot/sybreon/aemb/sw/cc/aemb/core.hh,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- core.hh 9 Apr 2008 19:48:37 -0000 1.1
+++ core.hh 26 Apr 2008 19:31:35 -0000 1.2
@@ -1,4 +1,4 @@
-/* $Id: core.hh,v 1.1 2008/04/09 19:48:37 sybreon Exp $
+/* $Id: core.hh,v 1.2 2008/04/26 19:31:35 sybreon Exp $
**
** AEMB2 HI-PERFORMANCE CPU
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -37,14 +37,18 @@
/**
Unique namespace for all aemb library functions
*/
+#ifdef __cplusplus
namespace aemb {
-
}
+#endif
#endif
/*
$Log: core.hh,v $
+ Revision 1.2 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
Revision 1.1 2008/04/09 19:48:37 sybreon
Added new C++ files
1.4 aemb/sw/cc/aemb/heap.hh
http://www.opencores.org/cvsweb.shtml/aemb/sw/cc/aemb/heap.hh.diff?r1=1.3&r2=1.4
(In the diff below, changes in quantity of whitespace are not shown.)
Index: heap.hh
===================================================================
RCS file: /cvsroot/sybreon/aemb/sw/cc/aemb/heap.hh,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- heap.hh 26 Apr 2008 18:05:22 -0000 1.3
+++ heap.hh 26 Apr 2008 19:31:35 -0000 1.4
@@ -1,4 +1,4 @@
-/* $Id: heap.hh,v 1.3 2008/04/26 18:05:22 sybreon Exp $
+/* $Id: heap.hh,v 1.4 2008/04/26 19:31:35 sybreon Exp $
**
** AEMB2 HI-PERFORMANCE CPU
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -27,7 +27,9 @@
#ifndef AEMB_HEAP_HH
#define AEMB_HEAP_HH
+#ifdef __cplusplus
namespace aemb {
+#endif
/**
Extracts the heap size from the linker
@@ -65,13 +67,17 @@
return tmp;
}
+#ifdef __cplusplus
}
-
+#endif
#endif
/*
$Log: heap.hh,v $
+ Revision 1.4 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
Revision 1.3 2008/04/26 18:05:22 sybreon
Minor cosmetic changes.
1.7 aemb/sw/cc/aemb/hook.hh
http://www.opencores.org/cvsweb.shtml/aemb/sw/cc/aemb/hook.hh.diff?r1=1.6&r2=1.7
(In the diff below, changes in quantity of whitespace are not shown.)
Index: hook.hh
===================================================================
RCS file: /cvsroot/sybreon/aemb/sw/cc/aemb/hook.hh,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- hook.hh 26 Apr 2008 18:04:31 -0000 1.6
+++ hook.hh 26 Apr 2008 19:31:35 -0000 1.7
@@ -1,4 +1,4 @@
-/* $Id: hook.hh,v 1.6 2008/04/26 18:04:31 sybreon Exp $
+/* $Id: hook.hh,v 1.7 2008/04/26 19:31:35 sybreon Exp $
**
** AEMB2 HI-PERFORMANCE CPU
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -34,8 +34,10 @@
#ifndef AEMB_HOOK_HH
#define AEMB_HOOK_HH
+#ifdef __cplusplus
namespace aemb {
extern "C" {
+#endif
void _program_init();
void _program_clean();
@@ -46,7 +48,9 @@
//void __env_lock(struct _reent *reent);
//void __env_unlock(struct _reent *reent);
+#ifdef __cplusplus
}
+#endif
/**
Finalisation hook
@@ -90,7 +94,7 @@
(int *)getStack(),
(int *)getStackTop);
signalMutex(); // exit critical section
- while (true) asm volatile ("nop"); // lock thread
+ while (1) asm volatile ("nop"); // lock thread
}
signalMutex(); // exit critical section
@@ -122,7 +126,9 @@
signalMutex();
}
+#ifdef __cplusplus
}
+#endif
#endif
@@ -135,6 +141,9 @@
/*
$Log: hook.hh,v $
+ Revision 1.7 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
Revision 1.6 2008/04/26 18:04:31 sybreon
Updated software to freeze T0 and run T1.
1.7 aemb/sw/cc/aemb/msr.hh
http://www.opencores.org/cvsweb.shtml/aemb/sw/cc/aemb/msr.hh.diff?r1=1.6&r2=1.7
(In the diff below, changes in quantity of whitespace are not shown.)
Index: msr.hh
===================================================================
RCS file: /cvsroot/sybreon/aemb/sw/cc/aemb/msr.hh,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- msr.hh 26 Apr 2008 18:05:22 -0000 1.6
+++ msr.hh 26 Apr 2008 19:31:35 -0000 1.7
@@ -1,4 +1,4 @@
-/* $Id: msr.hh,v 1.6 2008/04/26 18:05:22 sybreon Exp $
+/* $Id: msr.hh,v 1.7 2008/04/26 19:31:35 sybreon Exp $
**
** AEMB2 HI-PERFORMANCE CPU
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -30,22 +30,23 @@
#ifndef AEMB_MSR_HH
#define AEMB_MSR_HH
+#ifdef __cplusplus
namespace aemb {
+#endif
- const int MSR_BE = 0x00000001; ///< Buslock Enable
- const int MSR_IE = 0x00000002; ///< Interrupt Enable
- const int MSR_C = 0x00000004; ///< Arithmetic Carry
- const int MSR_BIP = 0x00000008; ///< Break in Progress
-
- const int MSR_MTX = 0x00000010; ///< Hardware Mutex
- const int MSR_ICE = 0x00000020; ///< Instruction Cache Enable
- const int MSR_DZ = 0x00000040; ///< Division by Zero
- const int MSR_DCE = 0x00000080; ///< Data Cache Enable
-
- //const int MSR_HTE = 0x10000000; ///< Hardware Threads Enable
- const int MSR_PHA = 0x20000000; ///< Hardware Thread Phase
- const int MSR_HTX = 0x40000000; ///< Hardware Threads Extension
- const int MSR_CC = 0x80000004; ///< Carry Copy
+#define MSR_BE (1 << 0) ///< Buslock Enable
+#define MSR_IE (1 << 1) ///< Interrupt Enable
+#define MSR_C (1 << 2) ///< Arithmetic Carry
+#define MSR_BIP (1 << 3) ///< Break in Progress
+
+#define MSR_MTX (1 << 4) ///< Hardware Mutex
+#define MSR_ICE (1 << 5) ///< Instruction Cache Enable
+#define MSR_DZ (1 << 6) ///< Division by Zero
+#define MSR_DCE (1 << 7) ///< Data Cache Enable
+
+#define MSR_PHA (1 << 29) ///< Hardware Thread Phase
+#define MSR_HTX (1 << 30) ///< Hardware Threads Extension
+#define MSR_CC (1 << 31) ///< Carry Copy
/**
Read the value of the MSR register
@@ -69,16 +70,16 @@
asm volatile ("mts rmsr, %0"::"r"(rmsr));
}
-
/**
Read and clear the MSR
@param rmsk clear mask
@return msr value
*/
+
inline int clrMSR(const short rmsk)
{
int tmp;
- asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(rmsk));
+ //asm volatile ("msrclr %0, %1":"=r"(tmp):"K"(rmsk):"memory");
return tmp;
}
@@ -87,55 +88,61 @@
@param rmsk set mask
@return msr value
*/
+
inline int setMSR(const short rmsk)
{
int tmp;
- asm volatile ("msrset %0, %1":"=r"(tmp):"K"(rmsk));
+ //asm volatile ("msrset %0, %1":"=r"(tmp):"K"(rmsk):"memory");
return tmp;
}
/** Enable global interrupts */
inline void enableInterrupts()
{
- putMSR(getMSR() | MSR_IE);
+ asm volatile ("msrset r0, %0"::"K"(MSR_IE):"memory");
}
/** Disable global interrupts */
inline void disableInterrupts()
{
- putMSR(getMSR() & ~MSR_IE);
+ asm volatile ("msrclr r0, %0"::"K"(MSR_IE));
}
/** Enable data caches */
inline void enableDataCache()
{
- putMSR(getMSR() | MSR_DCE);
+ asm volatile ("msrset r0, %0"::"K"(MSR_DCE));
}
/** Disable data caches */
inline void disableDataCache()
{
- putMSR(getMSR() & ~MSR_DCE);
+ asm volatile ("msrclr r0, %0"::"K"(MSR_DCE));
}
/** Enable inst caches */
inline void enableInstCache()
{
- putMSR(getMSR() | MSR_ICE);
+ asm volatile ("msrset r0, %0"::"K"(MSR_ICE));
}
/** Disable inst caches */
inline void disableInstCache()
{
- putMSR(getMSR() & ~MSR_ICE);
+ asm volatile ("msrclr r0, %0"::"K"(MSR_ICE));
}
+#ifdef __cplusplus
}
+#endif
#endif
/*
$Log: msr.hh,v $
+ Revision 1.7 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
Revision 1.6 2008/04/26 18:05:22 sybreon
Minor cosmetic changes.
1.5 aemb/sw/cc/aemb/stack.hh
http://www.opencores.org/cvsweb.shtml/aemb/sw/cc/aemb/stack.hh.diff?r1=1.4&r2=1.5
(In the diff below, changes in quantity of whitespace are not shown.)
Index: stack.hh
===================================================================
RCS file: /cvsroot/sybreon/aemb/sw/cc/aemb/stack.hh,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -b -r1.4 -r1.5
--- stack.hh 26 Apr 2008 18:04:31 -0000 1.4
+++ stack.hh 26 Apr 2008 19:31:35 -0000 1.5
@@ -1,4 +1,4 @@
-/* $Id: stack.hh,v 1.4 2008/04/26 18:04:31 sybreon Exp $
+/* $Id: stack.hh,v 1.5 2008/04/26 19:31:35 sybreon Exp $
**
** AEMB2 HI-PERFORMANCE CPU
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -27,7 +27,9 @@
#ifndef AEMB_STACK_HH
#define AEMB_STACK_HH
+#ifdef __cplusplus
namespace aemb {
+#endif
/**
Reads the size of the memory space allocated for the stack in bytes.
@@ -111,12 +113,17 @@
}
}
+#ifdef __cplusplus
}
+#endif
#endif
/*
$Log: stack.hh,v $
+ Revision 1.5 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
Revision 1.4 2008/04/26 18:04:31 sybreon
Updated software to freeze T0 and run T1.
1.3 aemb/sw/cc/aemb/stdio.hh
http://www.opencores.org/cvsweb.shtml/aemb/sw/cc/aemb/stdio.hh.diff?r1=1.2&r2=1.3
(In the diff below, changes in quantity of whitespace are not shown.)
Index: stdio.hh
===================================================================
RCS file: /cvsroot/sybreon/aemb/sw/cc/aemb/stdio.hh,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- stdio.hh 26 Apr 2008 18:05:22 -0000 1.2
+++ stdio.hh 26 Apr 2008 19:31:35 -0000 1.3
@@ -1,4 +1,4 @@
-/* $Id: stdio.hh,v 1.2 2008/04/26 18:05:22 sybreon Exp $
+/* $Id: stdio.hh,v 1.3 2008/04/26 19:31:35 sybreon Exp $
**
** AEMB2 HI-PERFORMANCE CPU
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -32,7 +32,9 @@
#ifndef AEMB_STDIO_HH
#define AEMB_STDIO_HH
+#ifdef __cplusplus
extern "C" {
+#endif
/**
Default stdout prototype.
@@ -50,12 +52,17 @@
*/
char inbyte();
+#ifdef __cplusplus
}
+#endif
#endif
/*
$Log: stdio.hh,v $
+ Revision 1.3 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
Revision 1.2 2008/04/26 18:05:22 sybreon
Minor cosmetic changes.
1.8 aemb/sw/cc/aemb/thread.hh
http://www.opencores.org/cvsweb.shtml/aemb/sw/cc/aemb/thread.hh.diff?r1=1.7&r2=1.8
(In the diff below, changes in quantity of whitespace are not shown.)
Index: thread.hh
===================================================================
RCS file: /cvsroot/sybreon/aemb/sw/cc/aemb/thread.hh,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- thread.hh 26 Apr 2008 18:05:22 -0000 1.7
+++ thread.hh 26 Apr 2008 19:31:35 -0000 1.8
@@ -1,4 +1,4 @@
-/* $Id: thread.hh,v 1.7 2008/04/26 18:05:22 sybreon Exp $
+/* $Id: thread.hh,v 1.8 2008/04/26 19:31:35 sybreon Exp $
**
** AEMB2 HI-PERFORMANCE CPU
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -32,14 +32,16 @@
#ifndef AEMB_THREAD_HH
#define AEMB_THREAD_HH
+#ifdef __cplusplus
namespace aemb {
+#endif
/**
Checks to see if currently executing Thread 1
@return true if is Thread 1
*/
- inline bool isThread1()
+ inline int isThread1()
{
int rmsr = getMSR();
return ((rmsr & MSR_HTX) && (rmsr & MSR_PHA));
@@ -50,7 +52,7 @@
@return true if is Thread 0
*/
- inline bool isThread0()
+ inline int isThread0()
{
int rmsr = getMSR();
return ((rmsr & MSR_HTX) && (!(rmsr & MSR_PHA)));
@@ -60,7 +62,7 @@
Checks to see if it is multi-threaded or not.
@return true if thread capable
*/
- inline bool isThreaded()
+ inline int isThreaded()
{
int rmsr = getMSR();
return (rmsr & MSR_HTX);
@@ -136,12 +138,17 @@
}
}
+#ifdef __cplusplus
}
+#endif
#endif
/*
$Log: thread.hh,v $
+ Revision 1.8 2008/04/26 19:31:35 sybreon
+ Made headers C compatible.
+
Revision 1.7 2008/04/26 18:05:22 sybreon
Minor cosmetic changes.
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