|
Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Mar 31 16:44:09 CEST 2008
Subject: [cvs-checkins] MODIFIED: camellia-vhdl ...
Date: 00/08/03 31:16:44 Modified: camellia-vhdl/looping camellia.vhd camellia_tb.do
camellia_tb.vhd control.vhd
Added: camellia-vhdl/looping camellia_if.vhd
Log:
Modified the interface of the core, some bug correction, added a serial interface (16bit chunks)
Revision Changes Path
1.2 camellia-vhdl/looping/camellia.vhd
http://www.opencores.org/cvsweb.shtml/camellia-vhdl/looping/camellia.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: camellia.vhd
===================================================================
RCS file: /cvsroot/pfulgoni/camellia-vhdl/looping/camellia.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- camellia.vhd 25 Mar 2008 17:24:42 -0000 1.1
+++ camellia.vhd 31 Mar 2008 14:44:08 -0000 1.2
@@ -3,7 +3,7 @@
-- Designer: Paolo Fulgoni <pfulgoni@o...>
--
-- Create Date: 02/01/2008
--- Last Update: 03/06/2008
+-- Last Update: 03/28/2008
-- Project Name: camellia-vhdl
-- Description: Looping version of Camellia
--
@@ -31,13 +31,19 @@
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
+
data_in : in STD_LOGIC_VECTOR (0 to 127);
+ enc_dec : in STD_LOGIC;
+ data_rdy : in STD_LOGIC;
+ data_acq : out STD_LOGIC;
+
key : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
- new_key : in STD_LOGIC;
- enc_dec : in STD_LOGIC;
- input_rdy : in STD_LOGIC;
- data_out : out STD_LOGIC_VECTOR (0 to 127)
+ key_rdy : in STD_LOGIC;
+ key_acq : out STD_LOGIC;
+
+ data_out : out STD_LOGIC_VECTOR (0 to 127);
+ output_rdy : out STD_LOGIC
);
end camellia;
@@ -46,13 +52,15 @@
signal s_clk : STD_LOGIC;
signal s_reset : STD_LOGIC;
signal s_data_in : STD_LOGIC_VECTOR (0 to 127);
+ signal s_enc_dec : STD_LOGIC;
+ signal s_data_rdy : STD_LOGIC;
+ signal s_data_acq : STD_LOGIC;
signal s_key_in : STD_LOGIC_VECTOR (0 to 255);
signal s_k_len : STD_LOGIC_VECTOR (0 to 1);
- signal s_new_key : STD_LOGIC;
- signal s_enc_dec : STD_LOGIC;
- signal s_input_rdy : STD_LOGIC;
- signal s_nxt_input : STD_LOGIC;
+ signal s_key_rdy : STD_LOGIC;
+ signal s_key_acq : STD_LOGIC;
signal s_data_to : STD_LOGIC_VECTOR (0 to 127);
+ signal s_output_rdy : STD_LOGIC;
signal s_k1 : STD_LOGIC_VECTOR (0 to 63);
signal s_k2 : STD_LOGIC_VECTOR (0 to 63);
signal s_newdata : STD_LOGIC;
@@ -81,12 +89,15 @@
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
+ enc_dec : in STD_LOGIC;
+ data_rdy : in STD_LOGIC;
+ data_acq : out STD_LOGIC;
key_in : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
- new_key : in STD_LOGIC;
- enc_dec : in STD_LOGIC;
- input_rdy : in STD_LOGIC;
+ key_rdy : in STD_LOGIC;
+ key_acq : out STD_LOGIC;
data_to : out STD_LOGIC_VECTOR (0 to 127);
+ output_rdy : out STD_LOGIC;
k1 : out STD_LOGIC_VECTOR (0 to 63);
k2 : out STD_LOGIC_VECTOR (0 to 63);
newdata : out STD_LOGIC;
@@ -118,12 +129,15 @@
clk => s_clk,
reset => s_reset,
data_in => s_data_in,
+ enc_dec => s_enc_dec,
+ data_rdy => s_data_rdy,
+ data_acq => s_data_acq,
key_in => s_key_in,
k_len => s_k_len,
- new_key => s_new_key,
- enc_dec => s_enc_dec,
- input_rdy => s_input_rdy,
+ key_rdy => s_key_rdy,
+ key_acq => s_key_acq,
data_to => s_data_to,
+ output_rdy => s_output_rdy,
k1 => s_k1,
k2 => s_k2,
newdata => s_newdata,
@@ -136,11 +150,15 @@
s_clk <= clk;
s_reset <= reset;
s_data_in <= data_in;
+ s_enc_dec <= enc_dec;
+ s_data_rdy <= data_rdy;
s_key_in <= key;
s_k_len <= k_len;
- s_new_key <= new_key;
- s_enc_dec <= enc_dec;
- s_input_rdy <= input_rdy;
+ s_key_rdy <= key_rdy;
+
+ data_acq <= s_data_acq;
+ key_acq <= s_key_acq;
data_out <= s_data_from(64 to 127) & s_data_from(0 to 63);
+ output_rdy <= s_output_rdy;
end RTL;
1.2 camellia-vhdl/looping/camellia_tb.do
http://www.opencores.org/cvsweb.shtml/camellia-vhdl/looping/camellia_tb.do.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: camellia_tb.do
===================================================================
RCS file: /cvsroot/pfulgoni/camellia-vhdl/looping/camellia_tb.do,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- camellia_tb.do 25 Mar 2008 17:24:42 -0000 1.1
+++ camellia_tb.do 31 Mar 2008 14:44:08 -0000 1.2
@@ -16,6 +16,7 @@
add wave -HEX -ports /uut/CTRL/*
add wave /uut/CTRL/PS
add wave -divider "keys"
+add wave -HEX /uut/CTRL/reg_kl
add wave -HEX /uut/CTRL/reg_kr
add wave -HEX /uut/CTRL/reg_ka
add wave -HEX /uut/CTRL/reg_kb
@@ -23,6 +24,9 @@
add wave -HEX /uut/CTRL/reg_kr_s
add wave -HEX /uut/CTRL/reg_ka_s
add wave -HEX /uut/CTRL/reg_kb_s
+add wave -divider "other regs"
+add wave -HEX /uut/CTRL/reg_enc_dec
+add wave -HEX /uut/CTRL/reg_k_len
add wave -divider "datapath"
add wave -HEX -ports /uut/DP/*
run 1400 ns
1.2 camellia-vhdl/looping/camellia_tb.vhd
http://www.opencores.org/cvsweb.shtml/camellia-vhdl/looping/camellia_tb.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: camellia_tb.vhd
===================================================================
RCS file: /cvsroot/pfulgoni/camellia-vhdl/looping/camellia_tb.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- camellia_tb.vhd 25 Mar 2008 17:24:42 -0000 1.1
+++ camellia_tb.vhd 31 Mar 2008 14:44:08 -0000 1.2
@@ -3,7 +3,7 @@
-- Designer: Paolo Fulgoni <pfulgoni@o...>
--
-- Create Date: 02/19/2008
--- Last Update: 03/06/2008
+-- Last Update: 03/28/2008
-- Project Name: camellia-vhdl
-- Description: VHDL Test Bench for module camellia
--
@@ -38,24 +38,30 @@
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
+ enc_dec : in STD_LOGIC;
+ data_rdy : in STD_LOGIC;
+ data_acq : out STD_LOGIC;
key : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
- new_key : in STD_LOGIC;
- enc_dec : in STD_LOGIC;
- input_rdy : in STD_LOGIC;
- data_out : out STD_LOGIC_VECTOR (0 to 127)
+ key_rdy : in STD_LOGIC;
+ key_acq : out STD_LOGIC;
+ data_out : out STD_LOGIC_VECTOR (0 to 127);
+ output_rdy : out STD_LOGIC
);
end component;
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal data_in : STD_LOGIC_VECTOR (0 to 127);
+ signal enc_dec : STD_LOGIC;
+ signal data_rdy : STD_LOGIC;
+ signal data_acq : STD_LOGIC;
signal key : STD_LOGIC_VECTOR (0 to 255);
signal k_len : STD_LOGIC_VECTOR (0 to 1);
- signal new_key : STD_LOGIC;
- signal enc_dec : STD_LOGIC;
- signal input_rdy : STD_LOGIC;
+ signal key_rdy : STD_LOGIC;
+ signal key_acq : STD_LOGIC;
signal data_out : STD_LOGIC_VECTOR (0 to 127);
+ signal output_rdy : STD_LOGIC;
-- constants
constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";
@@ -68,27 +74,29 @@
begin
uut : camellia
- port map(clk, reset, data_in, key, k_len, new_key,
- enc_dec, input_rdy, data_out);
+ port map(clk, reset, data_in, enc_dec, data_rdy, data_acq,
+ key, k_len, key_rdy, key_acq, data_out, output_rdy);
tb : process
begin
reset <= '1';
wait for 15 ns;
reset <= '0';
+
data_in <= X"0123456789abcdeffedcba9876543210";
+ enc_dec <= ENC;
+ data_rdy <= '1';
key <= X"0123456789abcdeffedcba987654321000112233445566778899aabbccddeeff";
k_len <= KLEN_128;
- new_key <= '1';
- enc_dec <= '0';
- input_rdy <= '1';
- wait for 494 ns;
+ key_rdy <= '1';
+
+ wait until key_acq = '1';
+ key_rdy <= '0';
+
+ wait until data_acq = '1';
data_in <= X"67673138549669730857065648eabe43";
- key <= X"0123456789abcdeffedcba987654321000112233445566778899aabbccddeeff";
- k_len <= KLEN_128;
- new_key <= '0';
- enc_dec <= '1';
- input_rdy <= '1';
+ enc_dec <= DEC;
+
wait;
end process;
1.2 camellia-vhdl/looping/control.vhd
http://www.opencores.org/cvsweb.shtml/camellia-vhdl/looping/control.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: control.vhd
===================================================================
RCS file: /cvsroot/pfulgoni/camellia-vhdl/looping/control.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- control.vhd 25 Mar 2008 17:24:42 -0000 1.1
+++ control.vhd 31 Mar 2008 14:44:08 -0000 1.2
@@ -3,7 +3,7 @@
-- Designer: Paolo Fulgoni <pfulgoni@o...>
--
-- Create Date: 01/31/2008
--- Last Update: 03/25/2008
+-- Last Update: 03/28/2008
-- Project Name: camellia-vhdl
-- Description: Control unit and key handling
--
@@ -31,13 +31,19 @@
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
+
data_in : in STD_LOGIC_VECTOR (0 to 127);
+ enc_dec : in STD_LOGIC;
+ data_rdy : in STD_LOGIC;
+ data_acq : out STD_LOGIC;
+
key_in : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
- new_key : in STD_LOGIC;
- enc_dec : in STD_LOGIC;
- input_rdy : in STD_LOGIC;
+ key_rdy : in STD_LOGIC;
+ key_acq : out STD_LOGIC;
+
data_to : out STD_LOGIC_VECTOR (0 to 127); -- data to datapath
+ output_rdy : out STD_LOGIC;
k1 : out STD_LOGIC_VECTOR (0 to 63);
k2 : out STD_LOGIC_VECTOR (0 to 63);
newdata : out STD_LOGIC;
@@ -58,7 +64,9 @@
FL2,
SIX3a, SIX3b, SIX3c, SIX3d, SIX3e, SIX3f,
FL3,
- SIX4a, SIX4b, SIX4c, SIX4d, SIX4e, SIX4f);
+ SIX4a, SIX4b, SIX4c, SIX4d, SIX4e, SIX4f,
+ WT
+ );
signal PS, NS : STATUS;
type K1_TYPE is (SIG1, SIG2, SIG3, SIG4, SIG5, SIG6,
@@ -72,6 +80,7 @@
signal prexor_sel : PREXOR_TYPE;
-- keys
+ signal reg_kl : STD_LOGIC_VECTOR (0 to 127);
signal reg_kr : STD_LOGIC_VECTOR (0 to 127);
signal reg_ka : STD_LOGIC_VECTOR (0 to 127);
signal reg_kb : STD_LOGIC_VECTOR (0 to 127);
@@ -81,6 +90,9 @@
signal reg_ka_s : STD_LOGIC_VECTOR (0 to 127);
signal reg_kb_s : STD_LOGIC_VECTOR (0 to 127);
+ signal reg_k_len : STD_LOGIC_VECTOR (0 to 1);
+ signal reg_enc_dec : STD_LOGIC;
+
-- input constant
constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";
constant KLEN_192 : STD_LOGIC_VECTOR (0 to 1) := "01";
@@ -126,23 +138,25 @@
reg_kb_s(64 to 127) when others;
with postxor_sel select
- post_xor <= key_in(64 to 127) & key_in(0 to 63) when KL,
+ post_xor <= reg_kl_s(64 to 127) & reg_kl_s(0 to 63) when KL,
reg_ka_s(64 to 127) & reg_ka_s(0 to 63) when KA,
reg_kb_s(64 to 127) & reg_kb_s(0 to 63) when KB,
(others=>'0') when others;
with prexor_sel select
- pre_xor <= key_in(0 to 127) when KL,
+ pre_xor <= reg_kl_s when KL,
reg_kr_s when KR,
reg_ka_s when KA,
reg_kb_s when KB,
(others=>'0') when others;
- REGISTERS_UPDATE : process(PS)
+ REGISTERS_UPDATE : process(clk)
variable coming_from_key : STD_LOGIC;
begin
+ if (clk'event and clk = '1') then
case PS is
when RST =>
+ reg_kl <= (others=>'0');
reg_kr <= (others=>'0');
reg_ka <= (others=>'0');
reg_kb <= (others=>'0');
@@ -150,10 +164,17 @@
reg_kr_s <= (others=>'0');
reg_ka_s <= (others=>'0');
reg_kb_s <= (others=>'0');
+ reg_enc_dec <= '0';
+ reg_k_len <= (others=>'0');
+ key_acq <= '0';
+ data_acq <= '0';
+ output_rdy <= '0';
coming_from_key := '0';
when KEYa =>
coming_from_key := '1';
- reg_kl_s <= key_in(0 to 127); -- kl
+ reg_kl <= key_in(0 to 127);
+ reg_kl_s <= key_in(0 to 127);
+ reg_k_len <= k_len;
case k_len is
when KLEN_192 =>
reg_kr <= key_in(128 to 191) & not (key_in(128 to 191));
@@ -167,8 +188,10 @@
end case;
k1_sel <= SIG1;
when KEYb =>
+ key_acq <= '1';
k1_sel <= SIG2;
when KEYc =>
+ key_acq <= '0';
k1_sel <= SIG3;
when KEYd =>
k1_sel <= SIG4;
@@ -181,7 +204,7 @@
when SIX1a =>
if (enc_dec = ENC) then
if (coming_from_key = '1') then
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from;
else
@@ -191,17 +214,17 @@
else
reg_ka_s <= reg_ka;
reg_kb_s <= reg_kb;
- reg_kl_s <= key_in(0 to 127); --kl
+ reg_kl_s <= reg_kl;
reg_kr_s <= reg_kr;
end if;
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
else
k1_sel <= KB_L;
end if;
else -- DEC
if (coming_from_key = '1') then
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
reg_ka <= data_from;
reg_ka_s <= data_from(111 to 127) & data_from(0 to 110); -- >>> 17
else
@@ -219,20 +242,22 @@
end if;
k1_sel <= KL_R;
end if;
+ reg_enc_dec <= enc_dec;
when SIX1b =>
coming_from_key := '0';
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
end if;
else -- DEC
- k1_sel <= KL_L; -- for each value of k_len
+ k1_sel <= KL_L; -- for each value of reg_k_len
end if;
+ data_acq <= '1';
when SIX1c =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
@@ -241,28 +266,29 @@
end if;
else -- DEC
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
- k1_sel <= KA_R; -- for each value of k_len
+ k1_sel <= KA_R; -- for each value of reg_k_len
end if;
+ data_acq <= '0';
when SIX1d =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KR_R;
end if;
else -- DEC
- k1_sel <= KA_L; -- for each value of k_len
+ k1_sel <= KA_L; -- for each value of reg_k_len
end if;
when SIX1e =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KA_L;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
k1_sel <= KL_R;
else
@@ -271,18 +297,18 @@
end if;
end if;
when SIX1f =>
- if (enc_dec = ENC) then
+ if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KR_L;
end if;
end if;
when FL1 =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
@@ -294,7 +320,7 @@
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
k2_sel <= KL_L;
else
@@ -305,8 +331,8 @@
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
end if;
when SIX2a =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
@@ -315,7 +341,7 @@
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(111 to 127) & reg_ka_s(0 to 110); -- >>> 17
else
@@ -325,15 +351,15 @@
end if;
end if;
when SIX2b =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KB_R;
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
else
k1_sel <= KL_L;
@@ -341,8 +367,8 @@
end if;
end if;
when SIX2c =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
@@ -350,7 +376,7 @@
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
end if;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(111 to 127) & reg_kl_s(0 to 110); -- >>> 17
else
@@ -359,15 +385,15 @@
end if;
end if;
when SIX2d =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(15 to 127) & reg_kl_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
@@ -376,15 +402,15 @@
end if;
end if;
when SIX2e =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KA_L;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
@@ -393,18 +419,18 @@
end if;
end if;
when SIX2f =>
- if (enc_dec = ENC) then
+ if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KR_L;
end if;
end if;
when FL2 =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
@@ -413,7 +439,7 @@
k1_sel <= KL_L;
k2_sel <= KL_R;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
k2_sel <= KA_L;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
@@ -425,8 +451,8 @@
end if;
end if;
when SIX3a =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
@@ -434,7 +460,7 @@
reg_kr_s <= reg_kr_s(15 to 127) & reg_kr_s(0 to 14); -- <<< 15
end if;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KA_R;
@@ -442,8 +468,8 @@
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
end if;
when SIX3b =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
@@ -451,7 +477,7 @@
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
end if;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
@@ -459,8 +485,8 @@
end if;
end if;
when SIX3c =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
@@ -468,7 +494,7 @@
reg_kb_s <= reg_kb_s(15 to 127) & reg_kb_s(0 to 14); -- <<< 15
end if;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_R;
else
k1_sel <= KL_R;
@@ -476,14 +502,14 @@
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX3d =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
else
k1_sel <= KB_R;
end if;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KL_L;
else
k1_sel <= KL_L;
@@ -491,15 +517,15 @@
end if;
end if;
when SIX3e =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
else
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
end if;
k1_sel <= KL_L;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_R;
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
else
@@ -508,15 +534,15 @@
end if;
end if;
when SIX3f =>
- if (enc_dec = ENC) then
- if (k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else
reg_ka_s <= reg_ka_s(15 to 127) & reg_ka_s(0 to 14); -- <<< 15
end if;
k1_sel <= KL_R;
else -- DEC
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
k1_sel <= KA_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
else
@@ -525,7 +551,7 @@
end if;
end if;
when FL3 =>
- if (enc_dec = ENC) then
+ if (reg_enc_dec = ENC) then
k1_sel <= KA_L;
k2_sel <= KA_R;
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
@@ -537,7 +563,7 @@
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
when SIX4a =>
- if (enc_dec = ENC) then
+ if (reg_enc_dec = ENC) then
k1_sel <= KR_L;
reg_kr_s <= reg_kr_s(17 to 127) & reg_kr_s(0 to 16); -- <<< 17
else -- DEC
@@ -545,13 +571,13 @@
reg_ka_s <= reg_ka_s(113 to 127) & reg_ka_s(0 to 112); -- >>> 15
end if;
when SIX4b =>
- if (enc_dec = ENC) then
+ if (reg_enc_dec = ENC) then
k1_sel <= KR_R;
else -- DEC
k1_sel <= KA_L;
end if;
when SIX4c =>
- if (enc_dec = ENC) then
+ if (reg_enc_dec = ENC) then
k1_sel <= KA_L;
reg_ka_s <= reg_ka_s(17 to 127) & reg_ka_s(0 to 16); -- <<< 17
else -- DEC
@@ -559,7 +585,7 @@
reg_kr_s <= reg_kr_s(113 to 127) & reg_kr_s(0 to 112); -- >>> 15
end if;
when SIX4d =>
- if (enc_dec = ENC) then
+ if (reg_enc_dec = ENC) then
k1_sel <= KA_R;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
@@ -569,7 +595,7 @@
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX4e =>
- if (enc_dec = ENC) then
+ if (reg_enc_dec = ENC) then
k1_sel <= KL_L;
reg_kl_s <= reg_kl_s(17 to 127) & reg_kl_s(0 to 16); -- <<< 17
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
@@ -579,14 +605,15 @@
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
when SIX4f =>
- if (enc_dec = ENC) then
+ if (reg_enc_dec = ENC) then
k1_sel <= KL_R;
reg_kb_s <= reg_kb_s(17 to 127) & reg_kb_s(0 to 16); -- <<< 17
else -- DEC
k1_sel <= KB_L;
reg_kl_s <= reg_kl_s(113 to 127) & reg_kl_s(0 to 112); -- >>> 15
end if;
-
+ when WT =>
+ -- do nothing
end case;
if (PS = KEYa) then
@@ -604,7 +631,7 @@
if (enc_dec = ENC) then
prexor_sel <= KL;
else
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
prexor_sel <= KA;
else
prexor_sel <= KB;
@@ -616,8 +643,8 @@
case PS is
when SIX3f =>
- if (k_len = KLEN_128) then
- if (enc_dec = ENC) then
+ if (reg_k_len = KLEN_128) then
+ if (reg_enc_dec = ENC) then
postxor_sel <= KA;
else
postxor_sel <= KL;
@@ -626,7 +653,7 @@
postxor_sel <= ZERO;
end if;
when SIX4f =>
- if (enc_dec = ENC) then
+ if (reg_enc_dec = ENC) then
postxor_sel <= KB;
else
postxor_sel <= KL;
@@ -641,12 +668,18 @@
newdata <= '0';
end if;
+ if ((PS = SIX3f and reg_k_len = KLEN_128) or PS = SIX4f) then
+ output_rdy <= '1';
+ else
+ output_rdy <= '0';
+ end if;
+
if (PS = FL1 or PS = FL2 or PS = FL3) then
sel <= SEL_FL;
else
sel <= SEL_F;
end if;
-
+ end if;
end process;
STATE_UPDATE: process (clk)
@@ -662,13 +695,13 @@
end if;
end process;
- NEXT_STATE: process (PS, input_rdy, new_key)
+ NEXT_STATE: process (PS, data_rdy, key_rdy)
begin
case PS is
when RST =>
NS <= KEYa;
when KEYa =>
- if(input_rdy = '1') then
+ if(key_rdy = '1') then
NS <= KEYb;
else
NS <= KEYa;
@@ -678,7 +711,7 @@
when KEYc =>
NS <= KEYd;
when KEYd =>
- if (k_len = KLEN_128) then
+ if (reg_k_len = KLEN_128) then
NS <= SIX1a;
else
NS <= KEYe;
@@ -688,7 +721,7 @@
when KEYf =>
NS <= SIX1a;
when SIX1a =>
- if(input_rdy = '1') then
+ if(data_rdy = '1') then
NS <= SIX1b;
else
NS <= SIX1a;
@@ -730,11 +763,15 @@
when SIX3e =>
NS <= SIX3f;
when SIX3f =>
- if (k_len = KLEN_128) then
- if (new_key = '1') then
+ if (reg_k_len = KLEN_128) then
+ if (key_rdy = '1') then
NS <= KEYa;
else
+ if (data_rdy = '1') then
NS <= SIX1a;
+ else
+ NS <= WT;
+ end if;
end if;
else
NS <= FL3;
@@ -752,13 +789,27 @@
when SIX4e =>
NS <= SIX4f;
when SIX4f =>
- if (new_key = '1') then
+ if (key_rdy = '1') then
NS <= KEYa;
else
+ if (data_rdy = '1') then
NS <= SIX1a;
+ else
+ NS <= WT;
end if;
- when others =>
- NS <= RST;
+ end if;
+ when WT =>
+ if (key_rdy = '1') then
+ NS <= KEYa;
+ else
+ if (data_rdy = '1') then
+ NS <= SIX1a;
+ else
+ NS <= WT;
+ end if;
+ end if;
+-- when others =>
+-- NS <= RST;
end case;
end process;
1.1 camellia-vhdl/looping/camellia_if.vhd
http://www.opencores.org/cvsweb.shtml/camellia-vhdl/looping/camellia_if.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: camellia_if.vhd
===================================================================
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <pfulgoni@o...>
--
-- Create Date: 03/25/2008
-- Last Update: 03/28/2008
-- Project Name: camellia-vhdl
-- Description: Interface to the Camellia core
--
-- Copyright (C) 2008 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity CAMELLIA_IF is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 15);
enc_dec : in STD_LOGIC;
en_data : in STD_LOGIC;
next_data : out STD_LOGIC;
key_in : in STD_LOGIC_VECTOR (0 to 15);
k_len : in STD_LOGIC_VECTOR (0 to 1);
en_key : in STD_LOGIC;
next_key : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (0 to 15);
out_rdy : out STD_LOGIC
);
end CAMELLIA_IF;
architecture RTL of CAMELLIA_IF is
component CAMELLIA is
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (0 to 127);
enc_dec : in STD_LOGIC;
data_rdy : in STD_LOGIC;
data_acq : out STD_LOGIC;
key : in STD_LOGIC_VECTOR (0 to 255);
k_len : in STD_LOGIC_VECTOR (0 to 1);
key_rdy : in STD_LOGIC;
key_acq : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (0 to 127);
output_rdy : out STD_LOGIC
);
end component;
signal s_clk : STD_LOGIC;
signal s_reset : STD_LOGIC;
signal s_data_in : STD_LOGIC_VECTOR (0 to 127);
signal s_enc_dec : STD_LOGIC;
signal s_data_rdy : STD_LOGIC;
signal s_data_acq : STD_LOGIC;
signal s_key : STD_LOGIC_VECTOR (0 to 255);
signal s_k_len : STD_LOGIC_VECTOR (0 to 1);
signal s_key_rdy : STD_LOGIC;
signal s_key_acq : STD_LOGIC;
signal s_data_out : STD_LOGIC_VECTOR (0 to 127);
signal s_output_rdy : STD_LOGIC;
signal key_count : STD_LOGIC_VECTOR (3 downto 0);
signal din_count : STD_LOGIC_VECTOR (2 downto 0);
signal dout_count : STD_LOGIC_VECTOR (2 downto 0);
signal reg_key : STD_LOGIC_VECTOR (0 to 255);
signal reg_din : STD_LOGIC_VECTOR (0 to 127);
signal reg_dout : STD_LOGIC_VECTOR (0 to 127);
signal int_out_rdy : STD_LOGIC;
-- input constant
constant KLEN_128 : STD_LOGIC_VECTOR (0 to 1) := "00";
constant KLEN_192 : STD_LOGIC_VECTOR (0 to 1) := "01";
constant KLEN_256 : STD_LOGIC_VECTOR (0 to 1) := "10";
begin
-- S-FUNCTION
core : CAMELLIA
port map(s_clk, s_reset, s_data_in, s_enc_dec, s_data_rdy,
s_data_acq, s_key, s_k_len, s_key_rdy, s_key_acq,
s_data_out, s_output_rdy);
KEY_PROC: process (reset, clk)
begin
if (reset = '1') then
next_key <= '1';
key_count <= "0000";
reg_key <= (others=>'0');
elsif (clk'event and clk = '1') then
if ((key_count = "0111" and k_len = KLEN_128) or
key_count = "1111") then
s_key_rdy <= '1';
elsif (s_key_acq = '1') then
s_key_rdy <= '0';
next_key <= '1';
end if;
if (en_key = '1') then
key_count <= key_count + "0001";
case k_len is
when KLEN_128 =>
reg_key <= reg_key(16 to 127) & key_in & X"00000000000000000000000000000000";
when KLEN_192 =>
reg_key <= reg_key(16 to 191) & key_in & X"0000000000000000";
when others =>
reg_key <= reg_key(16 to 255) & key_in;
end case;
else
key_count <= "0000";
end if;
end if;
end process;
DATA_IN_PROC: process (reset, clk)
begin
if (reset = '1') then
next_data <= '1';
din_count <= "000";
reg_din <= (others=>'0');
elsif (clk'event and clk = '1') then
if (din_count = "111") then
s_data_rdy <= '1';
elsif (s_data_acq = '1') then
s_data_rdy <= '0';
next_data <= '1';
end if;
if (en_data = '1') then
din_count <= din_count + "001";
reg_din <= reg_din(16 to 127) & data_in;
else
din_count <= "000";
end if;
end if;
end process;
DATA_OUT_PROC: process (reset, clk)
begin
if (reset = '1') then
dout_count <= "000";
int_out_rdy <= '0';
reg_dout <= (others=>'0');
elsif (clk'event and clk = '1') then
if (s_output_rdy = '1' and int_out_rdy = '0') then
dout_count <= "000";
reg_dout <= s_data_out;
int_out_rdy<= '1';
end if;
if (int_out_rdy = '1') then
if (dout_count /= "111") then
dout_count <= dout_count + "001";
reg_dout <= reg_dout(16 to 127) & X"0000"; -- <<< 16
else
int_out_rdy <= '0';
end if;
end if;
end if;
end process;
s_clk <= clk;
s_reset <= reset;
s_data_in <= reg_din;
s_enc_dec <= enc_dec;
s_key <= reg_key;
s_k_len <= k_len;
data_out <= reg_dout(0 to 15);
out_rdy <= int_out_rdy;
end RTL;
|
 |
Browse
