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From: cvs at opencores.org<cvs@o...>
Date: Fri Mar 28 05:44:28 CET 2008
Subject: [cvs-checkins] MODIFIED: mips789 ...
Date: 00/08/03 28:05:44

Modified: mips789/rtl/verilog wb_if.v
Log:
no message


Revision Changes Path
1.2 mips789/rtl/verilog/wb_if.v

http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/wb_if.v.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: wb_if.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/wb_if.v,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- wb_if.v 27 Mar 2008 15:05:22 -0000 1.1
+++ wb_if.v 28 Mar 2008 04:44:28 -0000 1.2
@@ -35,11 +35,53 @@
endmodule
*/

+
module b_d_save( // Added by Liwei 2008,3,17
input clk,
input pause ,
input [31:0] din,
output reg [31:0] dout);
+
+ wire [31:0] w32_1;
+ wire w1;
+ wire [31:0] w32_2;
+ r32_reg_clr_cls r32(
+ .r32_i(din),
+ .r32_o(w32_1),
+ .clk(clk),
+ // .cls(w1),
+ .cls(pause),
+ .clr(0)
+ );
+ r32_reg_clr_cls r32_1(
+ .r32_i(w32_1),
+ .r32_o(w32_2),
+ .clk(clk),
+ // .cls(w1),
+ .cls(pause),
+ .clr(0)
+ );
+ r1_reg_clr_cls r1(
+ .r1_i(pause),
+ .r1_o(w1),
+ .clk(clk),
+ .cls(0),
+ .clr(0)
+ );
+ always @(*)
+ if (pause==0)
+ dout=din;
+ else
+ dout=w32_2;
+
+endmodule
+
+
+module b_d_save1( // Added by Liwei 2008,3,17
+ input clk,
+ input pause ,
+ input [31:0] din,
+ output reg [31:0] dout);
/* reg lpause;
always @(posedge clk)lpause = pause ;