|
Message
From: cvs at opencores.org<cvs@o...>
Date: Thu Mar 27 16:05:22 CET 2008
Subject: [cvs-checkins] MODIFIED: mips789 ...
Date: 00/08/03 27:16:05 Modified: mips789/rtl/verilog ctl_fsm.v decode_pipe.v EXEC_stage.v
forward.v mem_module.v mips789_defs.v mips_core.v
mips_dvc.v mips_sys.v mips_top.v RF_components.v
RF_stage.v ulit.v
Added: mips789/rtl/verilog wb_if.v
Log:
Added global pause signal so as to add WISHBONE interface
Revision Changes Path
1.12 mips789/rtl/verilog/ctl_fsm.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/ctl_fsm.v.diff?r1=1.11&r2=1.12
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ctl_fsm.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/ctl_fsm.v,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -b -r1.11 -r1.12
--- ctl_fsm.v 23 Mar 2008 01:27:00 -0000 1.11
+++ ctl_fsm.v 27 Mar 2008 15:05:21 -0000 1.12
@@ -74,107 +74,110 @@
case (CurrState)
`IDLE:
begin
- if (~rst) NextState = `RST;
- else if ((irq)&&(~riack)) NextState = `IRQ;
- else if (id_cmd ==ID_NOI) NextState = `NOI;
- else if (id_cmd==ID_CUR) NextState = `CUR;
- else if (id_cmd==ID_MUL) NextState = `MUL;
- else if (id_cmd==ID_LD) NextState = `LD;
- else if (id_cmd==ID_RET) NextState = `RET;
- else NextState = `IDLE;
+ if (~rst) NextState =`__TP `RST;
+ else if ((irq)&&(~riack)) NextState = `__TP `IRQ;
+ else if (id_cmd ==ID_NOI) NextState =`__TP `NOI;
+ else if (id_cmd==ID_CUR) NextState =`__TP `CUR;
+ else if (id_cmd==ID_MUL) NextState =`__TP `MUL;
+ else if (id_cmd==ID_LD) NextState =`__TP `LD;
+ else if (id_cmd==ID_RET) NextState =`__TP `RET;
+ else NextState = `__TP`IDLE;
end
`NOI:
begin
- if (id_cmd ==ID_NOI) NextState = `NOI;
- else if (id_cmd==ID_CUR) NextState = `CUR;
- else if (id_cmd==ID_MUL) NextState = `MUL;
- else if (id_cmd==ID_LD) NextState = `LD;
- else if (id_cmd==ID_RET) NextState = `RET;
- else NextState = `IDLE;
+ if (id_cmd ==ID_NOI) NextState =`__TP `NOI;
+ else if (id_cmd==ID_CUR) NextState =`__TP `CUR;
+ else if (id_cmd==ID_MUL) NextState =`__TP `MUL;
+ else if (id_cmd==ID_LD) NextState =`__TP `LD;
+ else if (id_cmd==ID_RET) NextState =`__TP `RET;
+ else NextState = `__TP `IDLE;
end
- `CUR: NextState = `NOI;
- `RET: NextState = `IDLE;
- `IRQ: NextState = `IDLE;
- `RST: NextState = `IDLE;
- `LD: NextState = `IDLE;
- `MUL: NextState = (delay_counter==32)?`IDLE:`MUL;
- default NextState =`IDLE;
+ `CUR: NextState = `__TP `NOI;
+ `RET: NextState = `__TP `IDLE;
+ `IRQ: NextState =`__TP `IDLE;
+ `RST: NextState =`__TP `IDLE;
+ `LD: NextState = `__TP `IDLE;
+ `MUL: begin // NextState = (delay_counter==32)?`IDLE:`MUL;
+ if (delay_counter==32) NextState = `__TP `IDLE;
+ else NextState = `__TP `MUL;
+ end
+ default NextState =`__TP `IDLE;
endcase
end
always @ (*)/*Finite State Machine part3*/
begin
case (CurrState )
- `IDLE: begin id2ra_ins_clr = 1'b0;
- id2ra_ins_cls = 1'b0;
- id2ra_ctl_clr = 1'b0;
- id2ra_ctl_cls = 1'b0;
- ra2exec_ctl_clr = 1'b0;
+ `IDLE: begin id2ra_ins_clr = `__TP 1'b0;
+ id2ra_ins_cls = `__TP 1'b0;
+ id2ra_ctl_clr = `__TP 1'b0;
+ id2ra_ctl_cls = `__TP 1'b0;
+ ra2exec_ctl_clr = `__TP 1'b0;
pc_prectl=PC_IGN;
zz_is_nop = 0;end
`MUL: begin
- id2ra_ins_clr = 1'b1;
- id2ra_ins_cls = 1'b0;
- id2ra_ctl_clr = 1'b1;
- id2ra_ctl_cls = 1'b0;
- ra2exec_ctl_clr = 1'b0;
+ id2ra_ins_clr = `__TP 1'b1;
+ id2ra_ins_cls = `__TP 1'b0;
+ id2ra_ctl_clr = `__TP 1'b1;
+ id2ra_ctl_cls = `__TP 1'b0;
+ ra2exec_ctl_clr = `__TP 1'b0;
pc_prectl =PC_KEP;
zz_is_nop =0; end
`CUR: begin
- id2ra_ins_clr = 1'b0;
- id2ra_ins_cls = 1'b1;
- id2ra_ctl_clr = 1'b0;
- id2ra_ctl_cls = 1'b1;
- ra2exec_ctl_clr = 1'b1;
- pc_prectl =PC_KEP;
- zz_is_nop = 1; end
- `RET: begin id2ra_ins_clr = 1'b0;
- id2ra_ins_cls = 1'b0;
- id2ra_ctl_clr = 1'b0;
- id2ra_ctl_cls = 1'b0;
- ra2exec_ctl_clr = 1'b0;
- pc_prectl =PC_IGN;
- zz_is_nop = 1'b0; end
+ id2ra_ins_clr = `__TP 1'b0;
+ id2ra_ins_cls = `__TP 1'b1;
+ id2ra_ctl_clr = `__TP 1'b0;
+ id2ra_ctl_cls = `__TP 1'b1;
+ ra2exec_ctl_clr = `__TP 1'b1;
+ pc_prectl =`__TP PC_KEP;
+ zz_is_nop = `__TP 1; end
+ `RET: begin id2ra_ins_clr = `__TP 1'b0;
+ id2ra_ins_cls = `__TP 1'b0;
+ id2ra_ctl_clr = `__TP 1'b0;
+ id2ra_ctl_cls = `__TP 1'b0;
+ ra2exec_ctl_clr =`__TP 1'b0;
+ pc_prectl =`__TP PC_IGN;
+ zz_is_nop = `__TP 1'b0; end
`IRQ: begin
- id2ra_ins_clr = 1'b1;
- id2ra_ins_cls = 1'b0;
- id2ra_ctl_clr = 1'b1;
- id2ra_ctl_cls = 1'b0;
- ra2exec_ctl_clr = 1'b1;
- pc_prectl =PC_IRQ;
- zz_is_nop = 1'b0;end
+ id2ra_ins_clr = `__TP 1'b1;
+ id2ra_ins_cls = `__TP 1'b0;
+ id2ra_ctl_clr = `__TP 1'b1;
+ id2ra_ctl_cls = `__TP 1'b0;
+ ra2exec_ctl_clr = `__TP 1'b1;
+ pc_prectl =`__TP PC_IRQ;
+ zz_is_nop =`__TP 1'b0;end
`RST: begin
- id2ra_ins_clr = 1'b1;
- id2ra_ins_cls = 1'b0;
- id2ra_ctl_clr = 1'b1;
- id2ra_ctl_cls = 1'b0;
- ra2exec_ctl_clr = 1'b1;
- pc_prectl=PC_RST;
- zz_is_nop = 1'b1; end
+ id2ra_ins_clr = `__TP 1'b1;
+ id2ra_ins_cls = `__TP 1'b0;
+ id2ra_ctl_clr = `__TP 1'b1;
+ id2ra_ctl_cls = `__TP 1'b0;
+ ra2exec_ctl_clr =`__TP 1'b1;
+ pc_prectl=`__TP PC_RST;
+ zz_is_nop =`__TP 1'b1; end
`LD:begin
- id2ra_ins_clr = 1'b1;
- id2ra_ins_cls = 1'b0;
- id2ra_ctl_clr = 1'b1;
- id2ra_ctl_cls = 1'b0;
- ra2exec_ctl_clr = 1'b0;
- pc_prectl =PC_KEP;
- zz_is_nop = 1'b0;end
+ id2ra_ins_clr = `__TP 1'b1;
+ id2ra_ins_cls = `__TP 1'b0;
+ id2ra_ctl_clr = `__TP 1'b1;
+ id2ra_ctl_cls = `__TP 1'b0;
+ ra2exec_ctl_clr = `__TP 1'b0;
+ pc_prectl =`__TP PC_KEP;
+ zz_is_nop = `__TP 1'b0;end
`NOI:begin
- id2ra_ins_clr = 1'b0;
- id2ra_ins_cls = 1'b0;
- id2ra_ctl_clr = 1'b0;
- id2ra_ctl_cls = 1'b0;
- ra2exec_ctl_clr = 1'b0;
- pc_prectl=PC_IGN;
- zz_is_nop = 1'b0;end
+ id2ra_ins_clr = `__TP 1'b0;
+ id2ra_ins_cls =`__TP 1'b0;
+ id2ra_ctl_clr = `__TP 1'b0;
+ id2ra_ctl_cls = `__TP 1'b0;
+ ra2exec_ctl_clr = `__TP 1'b0;
+ pc_prectl=`__TP PC_IGN;
+ zz_is_nop =`__TP 1'b0;end
default begin
- id2ra_ins_clr = 1'b1;
- id2ra_ins_cls = 1'b0;
- id2ra_ctl_clr = 1'b1;
- id2ra_ctl_cls = 1'b0;
- ra2exec_ctl_clr = 1'b1;
- pc_prectl=PC_RST;
- zz_is_nop = 1'b1;end
+ id2ra_ins_clr =`__TP 1'b1;
+ id2ra_ins_cls = `__TP 1'b0;
+ id2ra_ctl_clr = `__TP 1'b1;
+ id2ra_ctl_cls = `__TP 1'b0;
+ ra2exec_ctl_clr = `__TP 1'b1;
+ pc_prectl=`__TP PC_RST;
+ zz_is_nop = `__TP 1'b1;end
endcase
end
endmodule
1.13 mips789/rtl/verilog/decode_pipe.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/decode_pipe.v.diff?r1=1.12&r2=1.13
(In the diff below, changes in quantity of whitespace are not shown.)
Index: decode_pipe.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/decode_pipe.v,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -b -r1.12 -r1.13
--- decode_pipe.v 23 Mar 2008 01:27:00 -0000 1.12
+++ decode_pipe.v 27 Mar 2008 15:05:21 -0000 1.13
@@ -1491,7 +1491,7 @@
output [1:0] rd_sel_o,
output [0:0] wb_mux_ctl_o,
output [0:0] wb_we_o
-) ;
+ ) ;
wire [4:0] BUS2040;
wire [0:0] BUS2048;
1.14 mips789/rtl/verilog/EXEC_stage.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/EXEC_stage.v.diff?r1=1.13&r2=1.14
(In the diff below, changes in quantity of whitespace are not shown.)
Index: EXEC_stage.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/EXEC_stage.v,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -b -r1.13 -r1.14
--- EXEC_stage.v 23 Mar 2008 01:27:00 -0000 1.13
+++ EXEC_stage.v 27 Mar 2008 15:05:21 -0000 1.14
@@ -27,16 +27,12 @@
input [1:0] muxa_ctl_i,
input [2:0] muxa_fw_ctl,
input [1:0] muxb_ctl_i,
- // input [2:0] muxb_fw_ctl,
input [31:0] pc_i,
input [31:0] rs_i,
input [31:0] rt_i,
output [31:0] alu_ur_o,
output [31:0] dmem_data_ur_o ,
output [31:0] zz_spc_o
-
-
-
);
wire [31:0] BUS2332;
1.12 mips789/rtl/verilog/forward.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/forward.v.diff?r1=1.11&r2=1.12
(In the diff below, changes in quantity of whitespace are not shown.)
Index: forward.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/forward.v,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -b -r1.11 -r1.12
--- forward.v 23 Mar 2008 01:27:31 -0000 1.11
+++ forward.v 27 Mar 2008 15:05:21 -0000 1.12
@@ -29,11 +29,21 @@
input alu_we,
input [4:0]mem_wr_rn,
input mem_we,
- output wire[2:0]mux_fw
- );
+ output reg [2:0]mux_fw
+ ) ;
+ /*
assign mux_fw = ((alu_we)&&(alu_wr_rn==rn)&&(alu_wr_rn!=0))?`FW_ALU:
((mem_we)&&(mem_wr_rn==rn)&&(mem_wr_rn!=0))?`FW_MEM:
`FW_NOP;
+
+ */
+ always @(*)
+ if ((alu_we)&&(alu_wr_rn==rn)&&(alu_wr_rn!=0))
+ mux_fw= `__TP `FW_ALU;
+ else if ((mem_we)&&(mem_wr_rn==rn)&&(mem_wr_rn!=0))
+ mux_fw=`__TP `FW_MEM;
+ else mux_fw= `__TP `FW_NOP;
+
endmodule
module fwd_mux(
1.12 mips789/rtl/verilog/mem_module.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mem_module.v.diff?r1=1.11&r2=1.12
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mem_module.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mem_module.v,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -b -r1.11 -r1.12
--- mem_module.v 23 Mar 2008 01:27:31 -0000 1.11
+++ mem_module.v 27 Mar 2008 15:05:21 -0000 1.12
@@ -126,7 +126,6 @@
.dout(dout_s)
);
- //
b_d_save uu3(
.clk(clk),
.pause(pause) ,
@@ -139,9 +138,6 @@
endmodule
-
-
-
module infile_dmem_ctl_reg(
input pause,
input clk,
@@ -175,45 +171,45 @@
`DMEM_SB:
begin
case(addr_i[1:0])
- 0:wr_en = 4'b1000;
- 1:wr_en = 4'b0100;
- 2:wr_en = 4'b0010;
- 3:wr_en = 4'b0001;
+ 0:wr_en = `__TP 4'b1000;
+ 1:wr_en = `__TP 4'b0100;
+ 2:wr_en = `__TP 4'b0010;
+ 3:wr_en = `__TP 4'b0001;
endcase
end
`DMEM_SH :
begin
case(addr_i[1:0])
- 'd0:wr_en=4'b1100;
- 'd2:wr_en=4'b0011;
- default :wr_en = 4'b0000;
+ 'd0:wr_en= `__TP 4'b1100;
+ 'd2:wr_en= `__TP 4'b0011;
+ default :wr_en = `__TP 4'b0000;
endcase
end
`DMEM_SWL :
begin
case(addr_i[1:0])
- 0:wr_en = 4'b0001;
- 1:wr_en = 4'b0011;
- 2:wr_en = 4'b0111;
- 3:wr_en = 4'b1111;
+ 0:wr_en = `__TP 4'b0001;
+ 1:wr_en = `__TP 4'b0011;
+ 2:wr_en = `__TP 4'b0111;
+ 3:wr_en = `__TP 4'b1111;
endcase
end
`DMEM_SWR :
begin
case(addr_i[1:0])
- 0:wr_en = 4'b1000;
- 1:wr_en = 4'b1100;
- 2:wr_en = 4'b1110;
- 3:wr_en = 4'b1111;
+ 0:wr_en = `__TP 4'b1000;
+ 1:wr_en = `__TP 4'b1100;
+ 2:wr_en = `__TP 4'b1110;
+ 3:wr_en = `__TP 4'b1111;
endcase
end
`DMEM_SW :
begin
- wr_en=4'b1111;
+ wr_en= `__TP 4'b1111;
end
- default wr_en=4'b0000;
+ default wr_en= `__TP 4'b0000;
endcase
endmodule
@@ -233,55 +229,55 @@
`DMEM_LBS :
case (byte_addr)
- 'd0:dout={{24{din[31]}},din[31:24]};
- 'd1:dout={{24{din[23]}},din[23:16]};
- 'd2:dout={{24{din[15]}},din[15:8]};
- 'd3:dout={{24{din[7]}},din[7:0] };
+ 'd0:dout= `__TP {{24{din[31]}},din[31:24]};
+ 'd1:dout= `__TP {{24{din[23]}},din[23:16]};
+ 'd2:dout= `__TP {{24{din[15]}},din[15:8]};
+ 'd3:dout= `__TP {{24{din[7]}},din[7:0] };
endcase
`DMEM_LBU :
case (byte_addr)
- 'd3:dout={24'b0,din[7:0]};
- 'd2:dout={24'b0,din[15:8]};
- 'd1:dout={24'b0,din[23:16]};
- 'd0:dout={24'b0,din[31:24]};
+ 'd3:dout= `__TP {24'b0,din[7:0]};
+ 'd2:dout= `__TP {24'b0,din[15:8]};
+ 'd1:dout= `__TP {24'b0,din[23:16]};
+ 'd0:dout= `__TP {24'b0,din[31:24]};
endcase
`DMEM_LHU :
case (byte_addr)
- 'd0:dout={16'b0,din[31:24],din[23:16]};
- 'd2:dout={16'b0,din[15:8],din[7 :0]};
- default:dout=32'bX;
+ 'd0:dout= `__TP {16'b0,din[31:24],din[23:16]};
+ 'd2:dout= `__TP {16'b0,din[15:8],din[7 :0]};
+ default:dout= `__TP 32'bX;
endcase
`DMEM_LHS :
case (byte_addr)
- 'd0 :dout={{16{din[31]}},din[31:24],din[23:16]};
- 'd2 :dout={{16{din[15]}},din[15:8],din[7 :0]};
- default:dout=32'bX;
+ 'd0 :dout= `__TP {{16{din[31]}},din[31:24],din[23:16]};
+ 'd2 :dout= `__TP {{16{din[15]}},din[15:8],din[7 :0]};
+ default:dout= `__TP 32'bX;
endcase
`DMEM_LWL :begin
case (byte_addr)
- 'd0:dout={din[31:24],rt_r[23:0]};
- 'd1:dout={din[31:16],rt_r[15:0]};
- 'd2:dout={din[31:8],rt_r[7:0]};
+ 'd0:dout= `__TP {din[31:24],rt_r[23:0]};
+ 'd1:dout= `__TP {din[31:16],rt_r[15:0]};
+ 'd2:dout= `__TP {din[31:8],rt_r[7:0]};
default :
- dout=din;
+ dout= `__TP din;
endcase
end
`DMEM_LWR : begin
case (byte_addr)
- 'd1:dout={rt_r[31:24],din[23:0]};
- 'd2:dout={rt_r[31:16],din[15:0]};
- 'd3:dout={rt_r[31:8],din[7:0]};
+ 'd1:dout= `__TP {rt_r[31:24],din[23:0]};
+ 'd2:dout= `__TP {rt_r[31:16],din[15:0]};
+ 'd3:dout= `__TP {rt_r[31:8],din[7:0]};
default :
- dout=din;
+ dout= `__TP din;
endcase
end
`DMEM_LW :
- dout=din;
+ dout= `__TP din;
default :
- dout=32'b0;
+ dout= `__TP 32'b0;
endcase
endmodule
@@ -296,13 +292,13 @@
case (ctl)
`DMEM_SB :
- dout={din[7:0],din[7:0],din[7:0],din[7:0]};
+ dout= `__TP {din[7:0],din[7:0],din[7:0],din[7:0]};
`DMEM_SH :
- dout = {din[15:0],din[15:0]};
+ dout = `__TP {din[15:0],din[15:0]};
`DMEM_SWL ,
`DMEM_SWR ,
`DMEM_SW :
- dout =din;
+ dout = `__TP din;
default dout=32'bX;
endcase
1.9 mips789/rtl/verilog/mips789_defs.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips789_defs.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips789_defs.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips789_defs.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- mips789_defs.v 23 Mar 2008 01:27:31 -0000 1.8
+++ mips789_defs.v 27 Mar 2008 15:05:21 -0000 1.9
@@ -195,6 +195,15 @@
+`define __TP
+//#1
+
+
+`define WB_INS_LATCH_ADDR 1
+
+`define WB_INS_LATCH_DATA ~`WB_INS_LATCH_ADDR
+
+ //
`define ALTERA
//this is DEBUG model ,
1.11 mips789/rtl/verilog/mips_core.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_core.v.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_core.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_core.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- mips_core.v 23 Mar 2008 01:27:31 -0000 1.10
+++ mips_core.v 27 Mar 2008 15:05:21 -0000 1.11
@@ -261,7 +261,7 @@
);
-
+ /*
r32_reg_clr_cls pc
(
.clr(0),
@@ -270,7 +270,26 @@
.r32_i(zz_pc_o),
.r32_o(BUS27031)
);
+ */
+
+
+ pc new_pc (
+ .clr(0),
+ .pause(pause),
+ .clk(clk),
+ .pc_i(zz_pc_o),
+ .pc_o(BUS27031)
+ );
+
+ /* module pc (
+ input clk,
+ input pause,
+ inout clr,
+ input [31:0] pc_i,
+ input [31:0] pc_o
+ );
+ */
r5_reg_clr_cls rnd_pass0
1.9 mips789/rtl/verilog/mips_dvc.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_dvc.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_dvc.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_dvc.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- mips_dvc.v 23 Mar 2008 01:27:31 -0000 1.8
+++ mips_dvc.v 27 Mar 2008 15:05:22 -0000 1.9
@@ -75,7 +75,8 @@
always @ (posedge clk)
begin
- if ( wr_dis_byte ) $display("HEX=>%x< CHAR=>%c<",din[7:0],din[7:0]);
+ if ( wr_dis_byte )
+ $display("HEX=>%x< CHAR=>%c<",din[7:0],din[7:0]);
end
wire wr_uartdata = addr==`UART_DATA_ADDR && sv_byte;
1.10 mips789/rtl/verilog/mips_sys.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_sys.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_sys.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_sys.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
1.7 mips789/rtl/verilog/mips_top.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_top.v.diff?r1=1.6&r2=1.7
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_top.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_top.v,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- mips_top.v 23 Mar 2008 01:27:30 -0000 1.6
+++ mips_top.v 27 Mar 2008 15:05:22 -0000 1.7
@@ -63,11 +63,9 @@
sim_mem_array sim_array//memory for simultion
`endif
- //assign pc_s=pc;
-
(
.clk(CLK),
- .pc_i(pc),
+ .pc_i(pc_s),
.ins_o(ins2core_s),
.wren(wr_en),
.din(data2mem),
@@ -76,13 +74,32 @@
);
- b_d_save u2u(
+ `if WB_INS_LATCH_ADDR
+
+ f_d_save ins_addr_keep(
+ .clk(CLK),
+ .pause(pause) ,
+ .din(pc),
+ .dout(pc_s)
+ );
+
+ // assign pc_s=pc;
+ assign ins2core =ins2core_s;
+
+ `else
+
+ b_d_save ins_data_keep(
.clk(CLK),
.pause(pause) ,
.din(ins2core_s),
.dout(ins2core)
);
+ assign pc_s=pc;
+ //assign ins2core =ins2core_s;
+
+ `endif
+
mips_sys isys
(
.pause(pause),
1.12 mips789/rtl/verilog/RF_components.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/RF_components.v.diff?r1=1.11&r2=1.12
(In the diff below, changes in quantity of whitespace are not shown.)
Index: RF_components.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/RF_components.v,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -b -r1.11 -r1.12
--- RF_components.v 23 Mar 2008 01:27:30 -0000 1.11
+++ RF_components.v 27 Mar 2008 15:05:22 -0000 1.12
@@ -25,13 +25,13 @@
always @ (*)
case (ctl)
- `EXT_SIGN :res ={sign,instr25_0[15:0]};//sign
- `EXT_UNSIGN :res ={16'b0,instr25_0[15:0]};//zeroext
- `EXT_J :res ={4'b0,instr25_0[25:0],2'b0};//jmp
- `EXT_B :res ={sign[13:0],instr25_0[15:0],2'B0};//branch
- `EXT_SA :res ={27'b0,instr25_0[10:6]} ;//sll,srl
- `EXT_S2H :res ={instr25_0[15:0],16'B0};//shift to high
- default: res=32'bx;
+ `EXT_SIGN :res = `__TP {sign,instr25_0[15:0]};//sign
+ `EXT_UNSIGN :res = `__TP {16'b0,instr25_0[15:0]};//zeroext
+ `EXT_J :res = `__TP {4'b0,instr25_0[25:0],2'b0};//jmp
+ `EXT_B :res = `__TP {sign[13:0],instr25_0[15:0],2'B0};//branch
+ `EXT_SA :res = `__TP {27'b0,instr25_0[10:6]} ;//sll,srl
+ `EXT_S2H :res = `__TP {instr25_0[15:0],16'B0};//shift to high
+ default: res= `__TP 32'bx;
endcase
endmodule
@@ -44,18 +44,19 @@
);
always @ (*)
case (ctl)
- `CMP_BEQ: res = (s==t);
- `CMP_BNE: res = (s!=t);
- `CMP_BLTZ: res = s[31];
- `CMP_BGTZ: res = ~s[31] && (|s[30:0]);
- `CMP_BLEZ: res = s[31] |(~|s);
- `CMP_BGEZ: res = ~s[31];
- default res=1'Bx;
+ `CMP_BEQ: res = `__TP (s==t);
+ `CMP_BNE: res = `__TP (s!=t);
+ `CMP_BLTZ: res = `__TP s[31];
+ `CMP_BGTZ: res = `__TP ~s[31] && (|s[30:0]);
+ `CMP_BLEZ: res = `__TP s[31] |(~|s);
+ `CMP_BGEZ: res = `__TP ~s[31];
+ default res= `__TP 1'Bx;
endcase
endmodule
module pc_gen(
+ input pause,
input [2:0]ctl,
output reg [31:0]pc_next,
input [3:0] pc_prectl,
@@ -69,13 +70,18 @@
wire [32:0] br_addr = pc + imm ;
always @ (*)
+ if (pause) pc_next = pc ;
+ else begin
if(pc_prectl == `PC_IGN )
begin
case (ctl)
- `PC_RET : pc_next = zz_spc ;
- `PC_J : pc_next ={pc[31:28],imm[27:0]};
- `PC_JR : pc_next = s;
- `PC_BC : pc_next = (check)?({br_addr[31:0]}):(pc+4);
+ `PC_RET : pc_next = `__TP zz_spc ;
+ `PC_J : pc_next = `__TP {pc[31:28],imm[27:0]};
+ `PC_JR : pc_next = `__TP s;
+ `PC_BC : begin // pc_next = (check)?({br_addr[31:0]}):(pc+4);
+ if (check)pc_next = `__TP {br_addr[31:0]};
+ else pc_next = `__TP pc+4;
+ end
default
/* `PC_NEXT :*/ pc_next = pc + 4 ;
endcase
@@ -83,13 +89,14 @@
else
begin
case (pc_prectl)
- `PC_KEP : pc_next=pc;
- `PC_IRQ : pc_next=irq;
+ `PC_KEP : pc_next= `__TP pc;
+ `PC_IRQ : pc_next= `__TP irq;
default
- /* `PC_RST : pc_next='d0;*/
- pc_next =0;
+ /* `PC_RST : pc_next= `__TP 'd0;*/
+ pc_next =`__TP 0;
endcase
end
+ end
endmodule
@@ -140,6 +147,7 @@
r_rdaddress_b <=rdaddress_b;
end
+
always@(posedge clock)
if (r_wren)
reg_bank[r_wraddress] <= r_data ;
@@ -152,4 +160,11 @@
((r_wraddress==r_rdaddress_b)&&(1==r_wren))?r_data:
reg_bank[r_rdaddress_b];
+
+
+ always@(posedge clock) //used only for debug
+ if((0==pause )&&(wren)&&(wraddress!=0))
+ begin
+ $display("%9d ns => Write to register : R%d = %x",$realtime*10,wraddress,data);
+ end
endmodule
1.11 mips789/rtl/verilog/RF_stage.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/RF_stage.v.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: RF_stage.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/RF_stage.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- RF_stage.v 23 Mar 2008 01:27:30 -0000 1.10
+++ RF_stage.v 27 Mar 2008 15:05:22 -0000 1.11
@@ -94,6 +94,7 @@
pc_gen i_pc_gen
(
+ .pause(0) ,
.check(NET904),
.ctl(pc_gen_ctl),
.imm(ext_o),
1.13 mips789/rtl/verilog/ulit.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/ulit.v.diff?r1=1.12&r2=1.13
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ulit.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/ulit.v,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -b -r1.12 -r1.13
--- ulit.v 23 Mar 2008 01:27:30 -0000 1.12
+++ ulit.v 27 Mar 2008 15:05:22 -0000 1.13
@@ -34,9 +34,9 @@
module add32(
input [31:0]d_i,
- output [31:0]d_o
+ output reg [31:0]d_o
);
- assign d_o = d_i + 4;
+ always@(*) d_o = `__TP d_i + 4;
endmodule
@@ -57,20 +57,24 @@
input [31:0]alu_i,
input [31:0]dmem_i,
input sel,
- output [31:0]wb_o
+ output reg [31:0]wb_o
);
-
+ /*
assign wb_o = (sel==`WB_MEM)?dmem_i:alu_i;
+ */
+ always@(*)
+ if (sel==`WB_MEM) wb_o = `__TP dmem_i;
+ else wb_o = `__TP alu_i ;
endmodule
module or32(
input [31:0]a,
input [31:0]b,
- output [31:0]c
+ output reg[31:0]c
);
- assign c = a|b ;
+ always@(*) c = `__TP a|b ;
endmodule
@@ -83,11 +87,11 @@
always @(*)
case (ctl)
- `RD_RD:rd_o=rd_i;
- `RD_RT:rd_o=rt_i;
- `RD_R31:rd_o='d31;
+ `RD_RD:rd_o= `__TP rd_i;
+ `RD_RT:rd_o= `__TP rt_i;
+ `RD_R31:rd_o= `__TP 'd31;
default :
- rd_o=0;
+ rd_o= `__TP 0;
endcase
endmodule
/*
@@ -214,36 +218,3 @@
*/
-
-
-
-
-
-module f_d_save( // Added by Liwei 2008,3,17
- input clk,
- input pause ,
- input [31:0] din,
- output reg [31:0] dout
- );
- reg [31:0] save_data; //temp register
- always @(posedge clk) //latch data at posedge of clk
- if (pause == 0 )save_data <= din;
-
- always@(*) //A MUX to select data for output port
- if (pause ==0 ) dout = din;
- else dout =save_data;
-endmodule
-
-module b_d_save( // Added by Liwei 2008,3,17
- input clk,
- input pause ,
- input [31:0] din,
- output reg [31:0] dout);
- reg lpause;
- always @(posedge clk)lpause = pause ;
- reg [31:0] save_data; //temp register
- always @(posedge clk) //latch data at posedge of clk
- if (lpause == 0)save_data <= din;
- always@(*) //A MUX to select data for output port
- if (lpause ==0 ) dout = din; else dout =save_data;
-endmodule
1.1 mips789/rtl/verilog/wb_if.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/wb_if.v?rev=1.1&content-type=text/x-cvsweb-markup
Index: wb_if.v
===================================================================
/// I am those days working on adding WISHBONE interface to this core .
// It now does now fully workes.
module f_d_save( // Added by Liwei 2008,3,17
input clk,
input pause ,
input [31:0] din,
output reg [31:0] dout
);
reg [31:0] save_data; //temp register
always @(posedge clk) //latch data at posedge of clk
if (pause == 0 )save_data <= din;
always@(*) //A MUX to select data for output port
if (pause ==0 ) dout = din;
else dout =save_data;
endmodule
/*
module b_d_save( // Added by Liwei 2008,3,17
input clk,
input pause ,
input [31:0] din,
output reg [31:0] dout);
reg lpause;
always @(posedge clk)lpause = pause ;
reg [31:0] save_data; //temp register
always @(posedge clk) //latch data at posedge of clk
if (lpause == 0)save_data <= din;
always@(*) //A MUX to select data for output port
if (lpause ==0 ) dout = din; else dout =save_data;
endmodule
*/
module b_d_save( // Added by Liwei 2008,3,17
input clk,
input pause ,
input [31:0] din,
output reg [31:0] dout);
/* reg lpause;
always @(posedge clk)lpause = pause ;
reg [31:0] save_data; //temp register
always @(posedge clk) //latch data at posedge of clk
if (lpause == 0)
save_data <= din;
always@(*) //A MUX to select data for output port
if (lpause ==0 ) dout = din; else dout =save_data;
*/
wire [31:0] w32;
wire w1;
r32_reg_clr_cls r32(
.r32_i(din),
.r32_o(w32),
.clk(clk),
.cls(w1),
.clr(0)
);
r1_reg_clr_cls r1(
.r1_i(pause),
.r1_o(w1),
.clk(clk),
.cls(0),
.clr(0)
);
always @(*)
if (w1==0)
dout=din;
else
dout=w32;
endmodule
module addr2sel(
input [31:0]data_addr,
output reg sel0,
output reg sel1,
output reg sel2,
output reg sel3,
output reg sel4,
output reg sel5,
output reg sel6,
output reg sel7,
output reg sel8
);
always @(*)
casex (data_addr[31:31-4])
4'b0xxx :{sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8} = 1<<8;
4'b1000 :{sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8} = 1<<7;
4'b1001 :{sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8} = 1<<6;
4'b1010 :{sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8} = 1<<5;
4'b1011 :{sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8} = 1<<4;
4'b1100 :{sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8} = 1<<3;
4'b1101 :{sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8} = 1<<2;
4'b1110 :{sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8} = 1<<1;
4'b1111 :{sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8} = 1;
default {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8} = 0;
endcase
endmodule
module sel_latch (
input sel0,
input sel1,
input sel2,
input sel3,
input sel4,
input sel5,
input sel6,
input sel7,
input sel8,
output lsel0,
output lsel1,
output lsel2,
output lsel3,
output lsel4,
output lsel5,
output lsel6,
output lsel7,
output lsel8,
input clk,
input pause
);
wire [8:0] w_lsel ;
assign lsel0 = w_lsel[0];
assign lsel1 = w_lsel[1];
assign lsel2 = w_lsel[2];
assign lsel3 = w_lsel[3];
assign lsel4 = w_lsel[4];
assign lsel5 = w_lsel[5];
assign lsel6 = w_lsel[6];
assign lsel7 = w_lsel[7];
assign lsel8 = w_lsel[8];
wire [8:0] sel_in = {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8};//,sel0sel0}
r9_reg_clr_cls sel_reg(
.r9_i(sel_in),
.r9_o(w_lsel),
.clk(clk),
.clr(0),
.cls(pause)
);
endmodule
module wb_ack_mux(
input lsel0,
input lsel1,
input lsel2,
input lsel3,
input lsel4,
input lsel5,
input lsel6,
input lsel7,
input lsel8,
input ack0 ,
input ack1 ,
input ack2 ,
input ack3 ,
input ack4 ,
input ack5 ,
input ack6 ,
input ack7 ,
input ack8 ,
output pause
);
wire [8:0] w_lsel = {lsel0,lsel1,lsel2,lsel3,lsel4,lsel5,lsel6,lsel7,lsel8 };
wire [8:0] w_ack = {ack0,ack1,ack2,ack3,ack4,ack5,ack6,ack7,ack8 } ;
assign pause = (w_lsel & w_ack)!=0 ;
endmodule
module wbbux_data_mux(
input din0,
input din1,
input din2,
input din3,
input din4,
input din5,
input din6,
input din7,
input din8,
output reg dout,
input sel0 ,
input sel1 ,
input sel2 ,
input sel3 ,
input sel4 ,
input sel5 ,
input sel6 ,
input sel7 ,
input sel8
);
wire [8:0] w_sel = {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7,sel8} ;
always @ (*)
case(w_sel)
1<<8:dout=din0;
1<<7:dout=din1;
1<<6:dout=din2;
1<<5:dout=din3;
1<<4:dout=din4;
1<<3:dout=din5;
1<<2:dout=din6;
1<<1:dout=din7;
1<<0:dout=din8;
default dout='bx;
endcase
endmodule
////////////////////////////////////
// In order to add pause signal,
// we need to modify pc
///////////////////////////////////
/*
module r1_reg_clr_cls(input[`R1_LEN-1:0] r1_i,output reg[`R1_LEN-1:0] r1_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r1_o<=0;else if(cls)r1_o<=r1_o;else r1_o<=r1_i;endmodule
*/
module pc (
input clk,
input pause,
input clr,
input [31:0] pc_i,
input [31:0] pc_o
);
wire lpause ;//links to the LATCH of pause ;
r1_reg_clr_cls pause_latch(
.r1_i(pause),
.r1_o(lpause ),
.cls(0),
.clr(clr),
.clk(clk)
);
wire pc_cls = lpause | pause ;
r32_reg_clr_cls pc_latch(
.r32_i(pc_i),
.r32_o(pc_o ),
.cls(pc_cls),
.clr(clr),
.clk(clk)
);
endmodule
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