Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Mon Mar 24 20:36:24 CET 2008
Subject: [cvs-checkins] MODIFIED: spi_slave ...
Date: 00/08/03 24:20:36

Modified: spi_slave/rtl/vhdl opb_spi_slave.vhd
Log:
added logic for CRC-Generation


Revision Changes Path
1.6 spi_slave/rtl/vhdl/opb_spi_slave.vhd

http://www.opencores.org/cvsweb.shtml/spi_slave/rtl/vhdl/opb_spi_slave.vhd.diff?r1=1.5&r2=1.6

(In the diff below, changes in quantity of whitespace are not shown.)

Index: opb_spi_slave.vhd
===================================================================
RCS file: /cvsroot/dkoethe/spi_slave/rtl/vhdl/opb_spi_slave.vhd,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -b -r1.5 -r1.6
--- opb_spi_slave.vhd 3 Dec 2007 20:28:35 -0000 1.5
+++ opb_spi_slave.vhd 24 Mar 2008 19:36:24 -0000 1.6
@@ -42,7 +42,8 @@
C_CPOL : integer range 0 to 1 := 0;
C_PHA : integer range 0 to 1 := 0;
C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 5; -- depth 32
- C_DMA_EN : boolean := false);
+ C_DMA_EN : boolean := false;
+ C_CRC_EN : boolean := false);

port (
-- OPB signals (Slave Side)
@@ -100,7 +101,8 @@
C_FAMILY : string;
C_SR_WIDTH : integer;
C_FIFO_SIZE_WIDTH : integer;
- C_DMA_EN : boolean);
+ C_DMA_EN : boolean;
+ C_CRC_EN : boolean);
port (
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);
@@ -132,7 +134,10 @@
opb_tx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);
opb_rx_dma_ctl : out std_logic_vector(0 downto 0);
- opb_rx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0));
+ opb_rx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
+ opb_rx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0);
+ opb_tx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0));
+
end component;


@@ -180,7 +185,8 @@
opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0);
opb_rx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
opb_rx_dma_done : out std_logic;
- opb_abort_flg : out std_logic);
+ opb_abort_flg : out std_logic;
+ opb_m_last_block : out std_logic);
end component;

component shift_register
@@ -241,6 +247,24 @@
opb_isr_clr : in std_logic);
end component;

+ component crc_core
+ generic (
+ C_SR_WIDTH : integer);
+ port (
+ rst : in std_logic;
+ opb_clk : in std_logic;
+ crc_en : in std_logic;
+ crc_clr : in std_logic;
+ opb_m_last_block : in std_logic;
+ fifo_rx_en : in std_logic;
+ fifo_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);
+ opb_rx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0);
+ fifo_tx_en : in std_logic;
+ fifo_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);
+ tx_crc_insert : out std_logic;
+ opb_tx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0));
+ end component;
+
-- opb_if
signal opb_ctl_reg : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);

@@ -259,12 +283,16 @@
signal opb_rx_dma_ctl : std_logic_vector(0 downto 0);
signal opb_rx_dma_num : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);

+ signal opb_rx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0);
+ signal opb_tx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0);
+
-- opb_m_if
signal opb_m_tx_en : std_logic;
signal opb_m_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
signal opb_m_rx_en : std_logic;
signal opb_m_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
signal opb_abort_flg : std_logic;
+ signal opb_m_last_block : std_logic; -- shift_register signal sr_tx_clk : std_logic; @@ -293,6 +321,11 @@ signal fifo_rx_en : std_logic; signal fifo_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0); + -- rx crc_core + signal crc_clr : std_logic; + signal crc_en : std_logic; + signal tx_crc_insert : std_logic; + begin -- behavior --* @@ -330,7 +363,8 @@ C_FAMILY => C_FAMILY, C_SR_WIDTH => C_SR_WIDTH, C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH, - C_DMA_EN => C_DMA_EN) + C_DMA_EN => C_DMA_EN, + C_CRC_EN => C_CRC_EN) port map ( OPB_ABus => OPB_ABus, OPB_BE => OPB_BE, @@ -362,7 +396,9 @@ opb_tx_dma_num => opb_tx_dma_num, opb_rx_dma_addr => opb_rx_dma_addr, opb_rx_dma_ctl => opb_rx_dma_ctl, - opb_rx_dma_num => opb_rx_dma_num); + opb_rx_dma_num => opb_rx_dma_num, + opb_rx_crc_value => opb_rx_crc_value, + opb_tx_crc_value => opb_tx_crc_value); --* OPB-Master-Interface --* @@ -413,7 +449,8 @@ opb_rx_dma_addr => opb_rx_dma_addr, opb_rx_dma_num => opb_rx_dma_num, opb_rx_dma_done => opb_fifo_flg(14), - opb_abort_flg => opb_abort_flg); + opb_abort_flg => opb_abort_flg, + opb_m_last_block => opb_m_last_block); end generate dma_enable; dma_disable : if (C_DMA_EN = false) generate @@ -484,7 +521,8 @@ underflow => opb_fifo_flg(5)); fifo_tx_en <= opb_s_tx_en or opb_m_tx_en; - fifo_tx_data <= opb_m_tx_data when (opb_tx_dma_ctl(0) = '1') else + fifo_tx_data <= opb_tx_crc_value when (C_CRC_EN and tx_crc_insert = '1') else + opb_m_tx_data when (opb_tx_dma_ctl(0) = '1') else opb_s_tx_data; --* Receive FIFO @@ -568,5 +606,30 @@ '0'; + ----------------------------------------------------------------------------- + + -- clear start_value at power up and soft_reset + crc_en <= opb_ctl_reg(C_OPB_CTL_REG_CRC_EN); + crc_clr <= opb_ctl_reg(C_OPB_CTL_REG_CRC_CLR) or rst; + + crc_gen : if (C_CRC_EN) generate + crc_core_1 : crc_core + generic map ( + C_SR_WIDTH => C_SR_WIDTH) + port map ( + rst => rst, + opb_clk => opb_clk, + crc_en => crc_en, + crc_clr => crc_clr, + opb_m_last_block => opb_m_last_block, + fifo_rx_en => fifo_rx_en, + fifo_rx_data => fifo_rx_data, + opb_rx_crc_value => opb_rx_crc_value, + fifo_tx_en => fifo_tx_en, + fifo_tx_data => fifo_tx_data, + tx_crc_insert => tx_crc_insert, + opb_tx_crc_value => opb_tx_crc_value); + end generate crc_gen; + end behavior;