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From: cvs at opencores.org<cvs@o...>
Date: Mon Mar 24 20:35:46 CET 2008
Subject: [cvs-checkins] MODIFIED: spi_slave ...
Date: 00/08/03 24:20:35

Modified: spi_slave/rtl/vhdl opb_m_if.vhd
Log:
added signal opb_m_last_block for CRC


Revision Changes Path
1.4 spi_slave/rtl/vhdl/opb_m_if.vhd

http://www.opencores.org/cvsweb.shtml/spi_slave/rtl/vhdl/opb_m_if.vhd.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: opb_m_if.vhd
===================================================================
RCS file: /cvsroot/dkoethe/spi_slave/rtl/vhdl/opb_m_if.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- opb_m_if.vhd 3 Dec 2007 20:22:02 -0000 1.3
+++ opb_m_if.vhd 24 Mar 2008 19:35:46 -0000 1.4
@@ -76,7 +76,8 @@
opb_rx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
opb_rx_dma_done : out std_logic;
---------------------------------------------------------------------------
- opb_abort_flg : out std_logic);
+ opb_abort_flg : out std_logic;
+ opb_m_last_block : out std_logic);
end opb_m_if;

architecture behavior of opb_m_if is
@@ -110,7 +111,6 @@
signal opb_rx_dma_done_int : std_logic;


-
begin -- behavior

--* convert M_DBus_big_end to little endian
@@ -177,6 +177,9 @@
opb_tx_dma_done_int <= '0';
opb_rx_dma_done_int <= '0';
opb_abort_flg <= '0';
+ opb_m_last_block <= '0';
+ opb_tx_dma_num_int <= (others => '0');
+ opb_rx_dma_num_int <= (others => '0');
elsif rising_edge(OPB_Clk) then
case state is
when idle =>
@@ -221,10 +224,16 @@
if (read_transfer) then
-- read
M_RNW <= '1';
+ if (conv_integer(opb_tx_dma_num_int) = 0) then
+ opb_m_last_block <= '1';
+ end if;
state <= transfer_read;
else
-- write
M_RNW <= '0';
+ if (conv_integer(opb_rx_dma_num_int) = 0) then
+ opb_m_last_block <= '1';
+ end if;
state <= transfer_write;
end if;
else
@@ -246,6 +255,7 @@
M_BE <= (others => '0');
if (conv_integer(opb_tx_dma_num_int) = 0) then
opb_tx_dma_done_int <= '1';
+ opb_m_last_block <= '0';
else
opb_tx_dma_num_int <= opb_tx_dma_num_int-1;
end if;
@@ -279,6 +289,7 @@
M_BE <= (others => '0');
if (conv_integer(opb_rx_dma_num_int) = 0) then
opb_rx_dma_done_int <= '1';
+ opb_m_last_block <= '0';
else
opb_rx_dma_num_int <= opb_rx_dma_num_int-1;
end if;