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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Mar 24 20:32:37 CET 2008
Subject: [cvs-checkins] MODIFIED: spi_slave ...
Date: 00/08/03 24:20:32 Added: spi_slave/rtl/vhdl crc_core.vhd crc_gen.vhd
Log:
Initial Release
Revision Changes Path
1.1 spi_slave/rtl/vhdl/crc_core.vhd
http://www.opencores.org/cvsweb.shtml/spi_slave/rtl/vhdl/crc_core.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: crc_core.vhd
===================================================================
library ieee;
use ieee.std_logic_1164.all;
entity crc_core is
generic (
C_SR_WIDTH : integer := 32);
port (
rst : in std_logic;
opb_clk : in std_logic;
crc_en : in std_logic;
crc_clr : in std_logic;
opb_m_last_block : in std_logic;
-- RX
fifo_rx_en : in std_logic;
fifo_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);
opb_rx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0);
-- TX
fifo_tx_en : in std_logic;
fifo_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);
tx_crc_insert : out std_logic;
opb_tx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0));
end crc_core;
architecture behavior of crc_core is
component crc_gen
generic (
C_SR_WIDTH : integer;
crc_start_value : std_logic_vector(31 downto 0));
port (
clk : in std_logic;
crc_clear : in std_logic;
crc_en : in std_logic;
crc_data_in : in std_logic_vector(C_SR_WIDTH-1 downto 0);
crc_data_out : out std_logic_vector(C_SR_WIDTH-1 downto 0));
end component;
signal rx_crc_en : std_logic;
signal tx_crc_en : std_logic;
type state_define is (idle,
insert_crc,
wait_last_block);
signal state : state_define;
signal cnt : integer range 0 to 15;
begin -- behavior
--* RX CRC_GEN
crc_gen_rx : crc_gen
generic map (
C_SR_WIDTH => C_SR_WIDTH,
crc_start_value => (others => '1'))
port map (
clk => OPB_Clk,
crc_clear => crc_clr,
crc_en => rx_crc_en,
crc_data_in => fifo_rx_data,
crc_data_out => opb_rx_crc_value);
-- disable crc_generation for last data block
rx_crc_en <= '1' when (crc_en = '1' and fifo_rx_en = '1' and opb_m_last_block = '0') else
'0';
-----------------------------------------------------------------------------
--* TX CRC_GEN
crc_gen_tx : crc_gen
generic map (
C_SR_WIDTH => C_SR_WIDTH,
crc_start_value => (others => '1'))
port map (
clk => OPB_Clk,
crc_clear => crc_clr,
crc_en => tx_crc_en,
crc_data_in => fifo_tx_data,
crc_data_out => opb_tx_crc_value);
-- disable crc_generation for last data block
tx_crc_en <= '1' when (crc_en = '1' and fifo_tx_en = '1' and opb_m_last_block = '0') else
'0';
process(rst, OPB_Clk)
begin
if (rst = '1') then
tx_crc_insert <= '0';
state <= idle;
elsif rising_edge(OPB_Clk) then
case state is
when idle=>
if (opb_m_last_block = '1' and crc_en = '1') then
cnt <= 15;
state <= insert_crc;
else
tx_crc_insert <= '0';
state <= idle;
end if;
when insert_crc =>
if (opb_m_last_block = '0') then
-- receive
state <= idle;
elsif (cnt = 0) then
tx_crc_insert <= '1';
state <= wait_last_block;
else
state <= insert_crc;
if (fifo_tx_en = '1') then
cnt <= cnt -1;
end if;
end if;
when wait_last_block =>
tx_crc_insert <= '0';
if (opb_m_last_block = '0') then
state <= idle;
else
state <= wait_last_block;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
end behavior;
1.1 spi_slave/rtl/vhdl/crc_gen.vhd
http://www.opencores.org/cvsweb.shtml/spi_slave/rtl/vhdl/crc_gen.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: crc_gen.vhd
===================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.PCK_CRC32_D32.all;
-- java -jar jacksum.jar -a crc:32,04C11DB7,FFFFFFFF,false,false,00000000
-- -q 000000000000000100000002000000030000000400000005000000060000000700000008000000090000000A0000000B0000000C0000000D0000000E0000000F
-- -x
-- Result: eb99fa90 64
use work.PCK_CRC8_D8.all;
-- java -jar jacksum.jar -a crc:8,07,FF,false,false,00
-- -q 000102030405060708090A0B0C0D0E0F
-- -x
-- Result: B8 16
entity crc_gen is
generic (
C_SR_WIDTH : integer := 32;
crc_start_value : std_logic_vector(31 downto 0) := (others => '1'));
port (
clk : in std_logic;
crc_clear : in std_logic;
crc_en : in std_logic;
crc_data_in : in std_logic_vector(C_SR_WIDTH-1 downto 0);
crc_data_out : out std_logic_vector(C_SR_WIDTH-1 downto 0));
end crc_gen;
architecture rtl of crc_gen is
signal crc_data_int : std_logic_vector(C_SR_WIDTH-1 downto 0);
begin -- crc_gen
process(clk)
begin
if rising_edge(clk) then
if (crc_clear = '1') then
crc_data_int <= crc_start_value(C_SR_WIDTH-1 downto 0);
elsif (crc_en = '1') then
case C_SR_WIDTH is
when 32 =>
crc_data_int <= nextCRC32_D32(crc_data_in, crc_data_int);
when 8 =>
crc_data_int <= nextCRC8_D8(crc_data_in, crc_data_int);
when others =>
-- no crc calculation
crc_data_int <= (others => '0');
end case;
end if;
end if;
end process;
crc_data_out <= crc_data_int;
end rtl;
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