|
Message
From: cvs at opencores.org<cvs@o...>
Date: Sun Mar 23 02:27:31 CET 2008
Subject: [cvs-checkins] MODIFIED: mips789 ...
Date: 00/08/03 23:02:27 Modified: mips789/rtl/verilog ulit.v RF_stage.v RF_components.v
mips_uart.v mips_top.v mips_sys.v mips_dvc.v
mips_core.v mips789_defs.v mem_module.v forward.v
Log:
no message
Revision Changes Path
1.12 mips789/rtl/verilog/ulit.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/ulit.v.diff?r1=1.11&r2=1.12
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ulit.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/ulit.v,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -b -r1.11 -r1.12
--- ulit.v 16 Mar 2008 09:27:42 -0000 1.11
+++ ulit.v 23 Mar 2008 01:27:30 -0000 1.12
@@ -140,7 +140,7 @@
module r32_reg_clr_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r32_o<=0;else if(cls)r32_o<=r32_o;else r32_o<=r32_i;endmodule
- /*
+/*
module ext_ctl_reg_clr(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input clr);always@(posedge clk)if(clr)ext_ctl_o<=0;else ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg_clr(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input clr);always@(posedge clk)if(clr)rd_sel_o<=0;else rd_sel_o<=rd_sel_i;endmodule
@@ -211,4 +211,39 @@
module r32_reg_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input cls);always@(posedge clk)if(cls) r32_o<=r32_o;else r32_o<=r32_i;endmodule
- */
\ No newline at end of file
+*/
+
+
+
+
+
+
+
+module f_d_save( // Added by Liwei 2008,3,17
+ input clk,
+ input pause ,
+ input [31:0] din,
+ output reg [31:0] dout
+ );
+ reg [31:0] save_data; //temp register
+ always @(posedge clk) //latch data at posedge of clk
+ if (pause == 0 )save_data <= din;
+
+ always@(*) //A MUX to select data for output port
+ if (pause ==0 ) dout = din;
+ else dout =save_data;
+endmodule
+
+module b_d_save( // Added by Liwei 2008,3,17
+ input clk,
+ input pause ,
+ input [31:0] din,
+ output reg [31:0] dout);
+ reg lpause;
+ always @(posedge clk)lpause = pause ;
+ reg [31:0] save_data; //temp register
+ always @(posedge clk) //latch data at posedge of clk
+ if (lpause == 0)save_data <= din;
+ always@(*) //A MUX to select data for output port
+ if (lpause ==0 ) dout = din; else dout =save_data;
+endmodule
1.10 mips789/rtl/verilog/RF_stage.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/RF_stage.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: RF_stage.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/RF_stage.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- RF_stage.v 16 Mar 2008 05:31:18 -0000 1.9
+++ RF_stage.v 23 Mar 2008 01:27:30 -0000 1.10
@@ -48,8 +48,6 @@
) ;
-
-
wire NET6609;
wire NET6658;
wire NET7774;
@@ -75,8 +73,6 @@
.rst(rst_i)
);
-
-
ctl_FSM MAIN_FSM
(
.pause(pause),
@@ -164,18 +160,10 @@
.rd_i(BUS5421),
.rd_o(rd_index_o),
.rt_i(rt_n_o)
- );/*
- wire bank_sel;
- dly3clk bank_sel_dly
- (
- .r1_i(iack_o),
- .r1_o(bank_sel),
- .clk(clk),
- .rst(rst_i)
- );*/
+ );
reg_array reg_bank
- ( // .pause(pause),
+ ( .pause(pause),
.clock(clk),
.data(wb_din_i),
.qa(BUS6061),
@@ -184,8 +172,7 @@
.rdaddress_a(BUS3237),
.rdaddress_b(BUS3236),
.wraddress(wb_addr_i),
- .wren(wb_we_i)/*,
- .bank_sel(1'b0)*/
+ .wren(wb_we_i)
);
fwd_mux rf_fwd_rt
1.11 mips789/rtl/verilog/RF_components.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/RF_components.v.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: RF_components.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/RF_components.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- RF_components.v 16 Mar 2008 05:31:18 -0000 1.10
+++ RF_components.v 23 Mar 2008 01:27:30 -0000 1.11
@@ -96,26 +96,18 @@
module reg_array(
- data,
- wraddress,
- rdaddress_a,
- rdaddress_b,
- wren,
- clock,
- qa,
- qb,
- rd_clk_cls
-// pause
- // bank_sel
+ input pause,
+ input [31:0] data,
+ input [4:0] wraddress,
+ input [4:0] rdaddress_a,
+ input [4:0] rdaddress_b,
+ input rd_clk_cls,
+ input wren,
+ input clock,
+ output [31:0] qa,
+ output [31:0] qb
);
- // input pause;
- input [31:0] data;
- input [4:0] wraddress;
- input [4:0] rdaddress_a;
- input [4:0] rdaddress_b;
- // input bank_sel;
- input rd_clk_cls;
- input wren;
+
reg [31:0] r_data;
reg [4:0] r_wraddress;
@@ -123,9 +115,7 @@
reg [4:0] r_rdaddress_b;
reg r_wren;
- input clock;
- output [31:0] qa;
- output [31:0] qb;
+
reg [31:0]reg_bank[0:31];
integer i;
@@ -136,15 +126,15 @@
end
always@(posedge clock)
- // if( ~pause )
+ if(0==pause )
begin
r_data <=data;
r_wraddress<=wraddress;
r_wren<=wren;
end
- always@(posedge clock) // ||( 0==pause )
- if(( 0==rd_clk_cls ))
+ always@(posedge clock)
+ if(( 0==rd_clk_cls )&&( 0==pause ))
begin
r_rdaddress_a <=rdaddress_a;
r_rdaddress_b <=rdaddress_b;
1.10 mips789/rtl/verilog/mips_uart.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_uart.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_uart.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_uart.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- mips_uart.v 16 Mar 2008 05:31:18 -0000 1.9
+++ mips_uart.v 23 Mar 2008 01:27:30 -0000 1.10
@@ -44,23 +44,23 @@
integer uart_send;
-initial begin
+ initial begin
uart_send = $fopen("uart_send.txt");
-end
+ end
-always @ (txd_ld)
-begin
+ always @ (txd_ld)
+ begin
if (txd_ld)
begin
$fwrite( uart_send,"%c",din[7:0]);
$display("UART0 =>%c<",din[7:0]);
end
-end
+ end
uart_read uart_rd_tak(
.sync_reset(rst),
@@ -101,8 +101,6 @@
output txd,write_done;
output write_busy;
-
-
wire queue_full;
wire queing, read_request;
wire [7:0] queue_data;
1.6 mips789/rtl/verilog/mips_top.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_top.v.diff?r1=1.5&r2=1.6
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_top.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_top.v,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -b -r1.5 -r1.6
--- mips_top.v 26 Nov 2007 13:46:21 -0000 1.5
+++ mips_top.v 23 Mar 2008 01:27:30 -0000 1.6
@@ -14,6 +14,7 @@
`include "mips789_defs.v"
module mips_top (
+ input pause,
input clk,
input rst,
input ser_rxd,
@@ -47,6 +48,10 @@
wire sys_rst = rr_rst;
+
+ wire [31:0] pc_s ;
+ wire [31:0] ins2core_s;
+
`ifdef ALTERA
pll50 Ipll(
.inclk0(clk),
@@ -57,18 +62,30 @@
assign CLK = clk;//clock for simultation
sim_mem_array sim_array//memory for simultion
`endif
+
+ //assign pc_s=pc;
+
(
.clk(CLK),
.pc_i(pc),
- .ins_o(ins2core),
+ .ins_o(ins2core_s),
.wren(wr_en),
.din(data2mem),
.data_addr_i(mem_Addr),
.dout(data2core)
);
+
+ b_d_save u2u(
+ .clk(CLK),
+ .pause(pause) ,
+ .din(ins2core_s),
+ .dout(ins2core)
+ );
+
mips_sys isys
(
+ .pause(pause),
.zz_addr_o(mem_Addr),
.zz_din(data2core),
.zz_dout(data2mem),
1.9 mips789/rtl/verilog/mips_sys.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_sys.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_sys.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_sys.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- mips_sys.v 26 Nov 2007 13:46:21 -0000 1.8
+++ mips_sys.v 23 Mar 2008 01:27:31 -0000 1.9
@@ -16,73 +16,35 @@
module mips_sys (
+ input pause,
+ input key1,
+ input key2,
+
+ input clk,
+ input rst,
+
+ output [6:0] seg7led1,
+ output [6:0] seg7led2,
+
+ output [7:0]lcd_data,
+ output lcd_rs,
+ output lcd_rw ,
+ output lcd_en ,
+ output led1,
+ output led2,
+
+ input [31:0] zz_din,
+ input [31:0] zz_ins_i,
+ output [31:0] zz_addr_o,
+ output [31:0] zz_dout,
+ output [31:0] zz_pc_o,
+ output [3:0] zz_wr_en_o,
- zz_addr_o,
- zz_din,
- zz_dout,
- zz_ins_i,
- zz_pc_o,
- zz_wr_en_o ,
-
- clk,
- rst,
-
- ser_rxd,
- ser_txd,
-
- seg7led1,
- seg7led2 ,
-
- lcd_data,
- lcd_rs,
- lcd_rw,
- lcd_en,
-
- led1,
- led2,
-
- key1,
- key2
+ input ser_rxd,
+ output ser_txd
) ;
- input key1;
- input key2;
-
- input clk;
- wire clk;
-
- input rst;
- wire rst;
-
-
- output [6:0] seg7led1;
- wire [6:0] seg7led1;
- output [6:0] seg7led2;
- wire [6:0] seg7led2;
-
- output [7:0]lcd_data;
- output lcd_rs;
- output lcd_rw ;
- output lcd_en ;
- output led1;
- output led2;
-
-
- input [31:0] zz_din;
- wire [31:0] zz_din;
- input [31:0] zz_ins_i;
- wire [31:0] zz_ins_i;
- output [31:0] zz_addr_o;
- wire [31:0] zz_addr_o;
- output [31:0] zz_dout;
- wire [31:0] zz_dout;
- output [31:0] zz_pc_o;
- wire [31:0] zz_pc_o;
- output [3:0] zz_wr_en_o;
- wire [3:0] zz_wr_en_o;
- input ser_rxd;
- output ser_txd;
wire [31:0] cop_addr;
wire [3:0] cop_mem_ctl;
@@ -94,6 +56,7 @@
mips_core i_mips_core
(
+ .pause(pause),
.clk(clk_sys),
.cop_addr_o(cop_addr),
.cop_data_o(data2cop),
1.8 mips789/rtl/verilog/mips_dvc.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_dvc.v.diff?r1=1.7&r2=1.8
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_dvc.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_dvc.v,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- mips_dvc.v 18 Nov 2007 03:36:45 -0000 1.7
+++ mips_dvc.v 23 Mar 2008 01:27:31 -0000 1.8
@@ -71,6 +71,13 @@
wire ld_wd = (mem_ctl==`DMEM_LW);
+ wire wr_dis_byte = addr==`DIS_DATA_ADDR && sv_byte;
+
+ always @ (posedge clk)
+ begin
+ if ( wr_dis_byte ) $display("HEX=>%x< CHAR=>%c<",din[7:0],din[7:0]);
+ end
+
wire wr_uartdata = addr==`UART_DATA_ADDR && sv_byte;
wire wr_lcddata = addr==`LCD_DATA_ADDR && sv_byte;
wire rd_uartdata = addr==`UART_DATA_ADDR && ld_byte;
@@ -112,6 +119,9 @@
wire w_txd_busy;
wire w_rx_rdy;
+
+
+
always@(posedge clk )
if (~rst)
begin
@@ -126,6 +136,8 @@
dout<=0;
end
+
+
always @(posedge clk)
if (~rst)
begin
1.10 mips789/rtl/verilog/mips_core.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_core.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_core.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_core.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- mips_core.v 16 Mar 2008 09:27:42 -0000 1.9
+++ mips_core.v 23 Mar 2008 01:27:31 -0000 1.10
@@ -14,6 +14,7 @@
`include "mips789_defs.v"
module mips_core (
+ input pause,
input clk,
input irq_i,
input rst,
@@ -80,8 +81,7 @@
mem_module MEM_CTL
(
- .pause(0),
-// .rt_i(BUS9884),
+ .pause(pause),
.Zz_addr(zz_addr_o),
.Zz_dout(zz_dout),
.Zz_wr_en(zz_wr_en_o),
@@ -97,7 +97,7 @@
rf_stage iRF_stage
(
- .pause(0),
+ .pause(pause),
.clk(clk),
.cmp_ctl_i(BUS109),
.ext_ctl_i(BUS117),
@@ -145,7 +145,6 @@
.muxa_ctl_i(BUS5832),
.muxa_fw_ctl(BUS1158),
.muxb_ctl_i(BUS5840),
- .muxb_fw_ctl(BUS1196),
.pc_i(BUS27031),
.rs_i(BUS7101),
.rst(rst),
@@ -158,7 +157,8 @@
r32_reg_clr_cls alu_pass0
(
- .cls(pause),.clr(0),
+ .cls(pause),
+ .clr(0),
.clk(clk),
.r32_i(BUS9589),
.r32_o(cop_addr_o)
@@ -167,7 +167,9 @@
r32_reg_clr_cls alu_pass1
- ( .cls(pause),.clr(0),
+ (
+ .cls(pause),
+ .clr(0),
.clk(clk),
.r32_i(cop_addr_o),
.r32_o(BUS422)
@@ -185,7 +187,9 @@
r32_reg_clr_cls cop_data_reg
- ( .cls(pause),.clr(0),
+ (
+ .cls(pause),
+ .clr(0),
.clk(clk),
.r32_i(BUS9884),
.r32_o(cop_data_o)
@@ -195,6 +199,7 @@
r32_reg_clr_cls cop_dout_reg
(
+
.clr(0),
.cls(pause),
.clk(clk),
@@ -205,7 +210,8 @@
decode_pipe decoder_pipe
- ( .pause(0),
+ (
+ .pause(pause),
.alu_func_o(BUS6275),
.alu_we_o(NET767),
.clk(clk),
@@ -226,8 +232,6 @@
.wb_we_o(NET1375)
);
-
-
r32_reg_clr_cls ext_reg
(
.clr(0),
@@ -241,7 +245,7 @@
forward iforward
(
- .pause(0),
+ .pause(pause),
.alu_rs_fw(BUS1158),
.alu_rt_fw(BUS1196),
.alu_we(NET767),
@@ -271,6 +275,8 @@
r5_reg_clr_cls rnd_pass0
(
+ .clr(0),
+ .cls(pause),
.clk(clk),
.r5_i(BUS775),
.r5_o(BUS1726)
@@ -279,7 +285,8 @@
r5_reg_clr_cls rnd_pass1
- ( .clr(0),
+ (
+ .clr(0),
.cls(pause),
.clk(clk),
.r5_i(BUS1726),
@@ -289,7 +296,8 @@
r5_reg_clr_cls rnd_pass2
- ( .clr(0),
+ (
+ .clr(0),
.cls(pause),
.clk(clk),
.r5_i(BUS1724),
@@ -310,7 +318,8 @@
r32_reg_clr_cls rt_reg
- ( .clr(0),
+ (
+ .clr(0),
.cls(pause),
.clk(clk),
.r32_i(BUS7160),
1.8 mips789/rtl/verilog/mips789_defs.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips789_defs.v.diff?r1=1.7&r2=1.8
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips789_defs.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips789_defs.v,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- mips789_defs.v 16 Mar 2008 09:27:42 -0000 1.7
+++ mips789_defs.v 23 Mar 2008 01:27:31 -0000 1.8
@@ -115,10 +115,14 @@
`define ALU_MTLO 30
`define ALU_MTHI 31
`define ALU_MULTU 8
- `define PC_IGN 1
+
+
+ `define PC_IGN 5
`define PC_KEP 2
`define PC_IRQ 4
`define PC_RST 8
+
+
`define PC_J 1
`define PC_JR 2
`define PC_BC 4
@@ -126,6 +130,8 @@
`define PC_NOP 0
`define PC_RET 6
`define PC_SPC 6
+
+
`define RF 13
`define EXEC 10
`define DMEM 4
@@ -181,6 +187,7 @@
`define TMR_DATA_ADDR 'H80_00_00_34
`define KEY1_IRQ_ADDR 'H80_00_00_2C
`define KEY2_IRQ_ADDR 'H80_00_00_30
+ `define DIS_DATA_ADDR 'H80_00_00_34
`define COUNTER_VALUE1 (`FRQ/`SER_RATE/2-1)
`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1)
@@ -188,9 +195,8 @@
-
`define ALTERA
-//this is DEBUG model ,
+ //this is DEBUG model ,
`else
1.11 mips789/rtl/verilog/mem_module.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mem_module.v.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mem_module.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mem_module.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- mem_module.v 16 Mar 2008 09:27:42 -0000 1.10
+++ mem_module.v 23 Mar 2008 01:27:31 -0000 1.11
@@ -15,7 +15,6 @@
module mem_module (
- //input [31:0] rt_i,
input pause,
input clk,
input [31:0] din,
@@ -28,21 +27,16 @@
output [31:0] dout
) ;
- /*module r32_reg_clr_cls(
- input[`R32_LEN-1:0] r32_i,
- output reg[`R32_LEN-1:0] r32_o,
- input clk,input clr,input cls
- );always@(posedge clk)if(clr) r32_o<=0;else if(cls)r32_o<=r32_o;else r32_o<=r32_i;endmodule
-
- */
wire [3:0] BUS512;
wire [1:0] BUS629;
- wire [31:0] BUS650;
+ wire [31:0] dmem_addr_i;
+ wire [31:0] dmem_addr_s;// = dmem_addr_i;
+ wire [3:0] dmem_ctl_s;
- wire [31:0]rt_r;
+ wire [31:0]rt_r;
r32_reg_clr_cls rt_latch(
.r32_i(din),
.r32_o(rt_r),
@@ -55,31 +49,73 @@
( .pause(pause),
.byte_addr_o(BUS629),
.clk(clk),
- .ctl_i(dmem_ctl),
+ .ctl_i(dmem_ctl_s),
.ctl_o(BUS512),
- .dmem_addr_i(BUS650)
+ .dmem_addr_i(dmem_addr_s)
);
-
-
mem_addr_ctl i_mem_addr_ctl
(
- .addr_i(BUS650),
- .ctl(dmem_ctl),
+ .addr_i(dmem_addr_s),
+ .ctl(dmem_ctl_s),
.wr_en(Zz_wr_en)
);
+ wire [31:0] din_s ;
mem_din_ctl i_mem_din_ctl
(
- .ctl(dmem_ctl),
- .din(din),
+ .ctl(dmem_ctl_s),
+ .din(din_s),
.dout(Zz_dout)
);
+ /*
+ comment this coz the save module will connect to data output.
+ mem_save u3u(
+ .clk(clk),
+ .pause(pause) ,
+ .din(din),
+ .dout(din_s)
+ );
+
+ */
+
+ assign din_s=din;
+
+ /*
+ comment this coz the save module will connect to data output.
+ mem_save u4u(
+ .clk(clk),
+ .pause(pause) ,
+ .din(dmem_ctl),
+ .dout(dmem_ctl_s)
+ );
+ */
+
+
+
+ assign dmem_ctl_s = dmem_ctl;
+
+ /*
+ comment this coz the save module will connect to data output.
+
+ mem_save uu(
+ .clk(clk),
+ .pause(pause) ,
+ .din(dmem_addr_i),
+ .dout(dmem_addr_s)
+ );
+ */
+ assign dmem_addr_s=dmem_addr_i;
+
+
+ wire [31:0]dout_s;
+
+
mem_dout_ctl i_mem_dout_ctl
(
@@ -87,16 +123,23 @@
.byte_addr(BUS629),
.ctl(BUS512),
.din(zZ_din),
+ .dout(dout_s)
+ );
+
+ //
+ b_d_save uu3(
+ .clk(clk),
+ .pause(pause) ,
+ .din(dout_s),
.dout(dout)
);
+ assign Zz_addr= dmem_addr_s;
+endmodule
- assign BUS650[31:0] = dmem_addr_i[31:0];
- assign Zz_addr[31:0] = BUS650[31:0];
-endmodule
module infile_dmem_ctl_reg(
@@ -112,7 +155,9 @@
assign byte_addr_i = dmem_addr_i[1:0] ;
always @(posedge clk)
- if(0==pause)
+ // if(0==pause)
+ //the registers in SYN_RAM does not pause so ,
+ //the latch for delay need not to pause either
begin
ctl_o<=(dmem_addr_i[31]==0)?ctl_i:0;
byte_addr_o<=byte_addr_i;
@@ -233,7 +278,6 @@
endcase
end
-
`DMEM_LW :
dout=din;
default :
@@ -255,25 +299,8 @@
dout={din[7:0],din[7:0],din[7:0],din[7:0]};
`DMEM_SH :
dout = {din[15:0],din[15:0]};
- `DMEM_SWL ,/*:
- begin
- case(addr_i[1:0])
- 0:dout = 4'b0001;
- 1:dout = 4'b0011;
- 2:dout = 4'b0111;
- 3:dout = 4'b1111;
- endcase
- end
- */
- `DMEM_SWR ,/* :
- begin
- case(addr_i[1:0])
- 0:dout = 4'b1000;
- 1:dout = 4'b1100;
- 2:dout = 4'b1110;
- 3:dout = 4'b1111;
- endcase
- end */
+ `DMEM_SWL ,
+ `DMEM_SWR ,
`DMEM_SW :
dout =din;
default dout=32'bX;
1.11 mips789/rtl/verilog/forward.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/forward.v.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: forward.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/forward.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- forward.v 16 Mar 2008 09:27:42 -0000 1.10
+++ forward.v 23 Mar 2008 01:27:31 -0000 1.11
@@ -48,13 +48,12 @@
`FW_ALU :dout=fw_alu;
`FW_MEM :dout=fw_dmem;
default
- /*`FW_NOP :dout=din;*/
dout=din;
endcase
endmodule
module forward (
-input pause,
+ input pause,
input alu_we,
input clk,
input mem_We,
@@ -67,9 +66,7 @@
output [2:0] cmp_rs_fw,
output [2:0] cmp_rt_fw,
output [2:0] dmem_fw
-) ;
-
-
+ ) ;
wire [2:0] BUS1345;
wire [4:0] BUS82;
@@ -125,19 +122,22 @@
r5_reg_clr_cls fw_reg_rns
(
- .clk(clk),.cls(pause),.clr(0),
+ .clk(clk),
+ .cls(pause),
+ .clr(0),
.r5_i(rns_i),
.r5_o(BUS82)
);
- r1_reg_clr_cls fw_reg_rnt
+ r5_reg_clr_cls fw_reg_rnt
(
-.cls(pause),.clr(0),
+ .cls(pause),
+ .clr(0),
.clk(clk),
- .r1_i(rnt_i),
- .r1_o(BUS937)
+ .r5_i(rnt_i),
+ .r5_o(BUS937)
);
|
 |
Browse
