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Message
From: cvs at opencores.org<cvs@o...>
Date: Sun Mar 23 02:27:01 CET 2008
Subject: [cvs-checkins] MODIFIED: mips789 ...
Date: 00/08/03 23:02:27 Modified: mips789/rtl/verilog EXEC_stage.v dvc.v decode_pipe.v
ctl_fsm.v
Log:
no message
Revision Changes Path
1.13 mips789/rtl/verilog/EXEC_stage.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/EXEC_stage.v.diff?r1=1.12&r2=1.13
(In the diff below, changes in quantity of whitespace are not shown.)
Index: EXEC_stage.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/EXEC_stage.v,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -b -r1.12 -r1.13
--- EXEC_stage.v 16 Mar 2008 09:27:42 -0000 1.12
+++ EXEC_stage.v 23 Mar 2008 01:27:00 -0000 1.13
@@ -14,50 +14,30 @@
`include "mips789_defs.v"
module exec_stage
- ( pause,
- clk,rst,spc_cls_i,alu_func,
- dmem_fw_ctl,ext_i,fw_alu,fw_dmem,
- muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,
- muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,
- dmem_data_ur_o,zz_spc_o
- );
- input pause;
- input clk;
- wire clk;
- input rst;
- wire rst;
- input spc_cls_i;
- wire spc_cls_i;
- input [4:0] alu_func;
- wire [4:0] alu_func;
- input [2:0] dmem_fw_ctl;
- wire [2:0] dmem_fw_ctl;
- input [31:0] ext_i;
- wire [31:0] ext_i;
- input [31:0] fw_alu;
- wire [31:0] fw_alu;
- input [31:0] fw_dmem;
- wire [31:0] fw_dmem;
- input [1:0] muxa_ctl_i;
- wire [1:0] muxa_ctl_i;
- input [2:0] muxa_fw_ctl;
- wire [2:0] muxa_fw_ctl;
- input [1:0] muxb_ctl_i;
- wire [1:0] muxb_ctl_i;
- input [2:0] muxb_fw_ctl;
- wire [2:0] muxb_fw_ctl;
- input [31:0] pc_i;
- wire [31:0] pc_i;
- input [31:0] rs_i;
- wire [31:0] rs_i;
- input [31:0] rt_i;
- wire [31:0] rt_i;
- output [31:0] alu_ur_o;
- wire [31:0] alu_ur_o;
- output [31:0] dmem_data_ur_o;
- wire [31:0] dmem_data_ur_o;
- output [31:0] zz_spc_o;
- wire [31:0] zz_spc_o;
+ (
+ input pause,
+ input clk,
+ input rst,
+ input spc_cls_i,
+ input [4:0] alu_func,
+ input [2:0] dmem_fw_ctl,
+ input [31:0] ext_i,
+ input [31:0] fw_alu,
+ input [31:0] fw_dmem,
+ input [1:0] muxa_ctl_i,
+ input [2:0] muxa_fw_ctl,
+ input [1:0] muxb_ctl_i,
+ // input [2:0] muxb_fw_ctl,
+ input [31:0] pc_i,
+ input [31:0] rs_i,
+ input [31:0] rt_i,
+ output [31:0] alu_ur_o,
+ output [31:0] dmem_data_ur_o ,
+ output [31:0] zz_spc_o
+
+
+
+ );
wire [31:0] BUS2332;
wire [31:0] BUS2446;
@@ -91,26 +71,13 @@
.din(rt_i)
);
- /* alu_muxb1 i_alu_muxb
- (
- .b_o(BUS468),
- .ctl(muxb_ctl_i),
- .ext(ext_i),
- .fw_alu(fw_alu),
- .fw_ctl(muxb_fw_ctl),
- .fw_mem(fw_dmem),
- .rt(rt_i)
- );
- */
+
alu_muxb i_alu_muxb
(
.b_o(BUS468),
.ctl(muxb_ctl_i),
.ext(ext_i),
- // .fw_alu(fw_alu),
- // .fw_ctl(muxb_fw_ctl),
- // .fw_mem(fw_dmem),
.rt(dmem_data_ur_o)
);
@@ -147,7 +114,8 @@
r32_reg_clr_cls spc
(
- .clk(clk),.clr(0),
+ .clk(clk),
+ .clr(0),
.cls(spc_cls_i|pause),
.r32_i(pc_i),
.r32_o(zz_spc_o)
@@ -194,7 +162,7 @@
.shift_func(ctl),
.shift_amount(a)
);
-*/ shifter_tak mips_shifter(
+ */ shifter_tak mips_shifter(
.a(b),
.shift_out(shift_c),
.shift_func(ctl),
1.10 mips789/rtl/verilog/dvc.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/dvc.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: dvc.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/dvc.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
1.12 mips789/rtl/verilog/decode_pipe.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/decode_pipe.v.diff?r1=1.11&r2=1.12
(In the diff below, changes in quantity of whitespace are not shown.)
Index: decode_pipe.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/decode_pipe.v,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -b -r1.11 -r1.12
--- decode_pipe.v 16 Mar 2008 09:27:42 -0000 1.11
+++ decode_pipe.v 23 Mar 2008 01:27:00 -0000 1.12
@@ -1157,69 +1157,38 @@
-module pipelinedregs (pause,
- clk,id2ra_ctl_clr,id2ra_ctl_cls,ra2ex_ctl_clr,
- alu_func_i,alu_we_i,cmp_ctl_i,dmem_ctl_i,ext_ctl_i,
- muxa_ctl_i,muxb_ctl_i,pc_gen_ctl_i,rd_sel_i,wb_mux_ctl_i,
- wb_we_i,alu_func_o,alu_we_o,cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,
- ext_ctl,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,wb_mux_ctl_o,wb_we_o
- ) ;
- input pause;
- input clk;
- wire clk;
- input id2ra_ctl_clr;
- wire id2ra_ctl_clr;
- input id2ra_ctl_cls;
- wire id2ra_ctl_cls;
- input ra2ex_ctl_clr;
- wire ra2ex_ctl_clr;
- input [4:0] alu_func_i;
- wire [4:0] alu_func_i;
- input [0:0] alu_we_i;
- wire [0:0] alu_we_i;
- input [2:0] cmp_ctl_i;
- wire [2:0] cmp_ctl_i;
- input [3:0] dmem_ctl_i;
- wire [3:0] dmem_ctl_i;
- input [2:0] ext_ctl_i;
- wire [2:0] ext_ctl_i;
- input [1:0] muxa_ctl_i;
- wire [1:0] muxa_ctl_i;
- input [1:0] muxb_ctl_i;
- wire [1:0] muxb_ctl_i;
- input [2:0] pc_gen_ctl_i;
- wire [2:0] pc_gen_ctl_i;
- input [1:0] rd_sel_i;
- wire [1:0] rd_sel_i;
- input [0:0] wb_mux_ctl_i;
- wire [0:0] wb_mux_ctl_i;
- input [0:0] wb_we_i;
- wire [0:0] wb_we_i;
- output [4:0] alu_func_o;
- wire [4:0] alu_func_o;
- output [0:0] alu_we_o;
- wire [0:0] alu_we_o;
- output [2:0] cmp_ctl_o;
- wire [2:0] cmp_ctl_o;
- output [3:0] dmem_ctl_o;
- wire [3:0] dmem_ctl_o;
- output [3:0] dmem_ctl_ur_o;
- wire [3:0] dmem_ctl_ur_o;
- output [2:0] ext_ctl;
- wire [2:0] ext_ctl;
- output [1:0] muxa_ctl_o;
- wire [1:0] muxa_ctl_o;
- output [1:0] muxb_ctl_o;
- wire [1:0] muxb_ctl_o;
- output [2:0] pc_gen_ctl_o;
- wire [2:0] pc_gen_ctl_o;
- output [1:0] rd_sel_o;
- wire [1:0] rd_sel_o;
- output [0:0] wb_mux_ctl_o;
- wire [0:0] wb_mux_ctl_o;
- output [0:0] wb_we_o;
- wire [0:0] wb_we_o;
+module pipelinedregs (
+
+ input pause,
+ input clk,
+ input id2ra_ctl_clr,
+ input id2ra_ctl_cls,
+ input ra2ex_ctl_clr,
+ input [4:0] alu_func_i,
+ input [0:0] alu_we_i,
+ input [2:0] cmp_ctl_i,
+ input [3:0] dmem_ctl_i,
+ input [2:0] ext_ctl_i,
+ input [1:0] muxa_ctl_i,
+ input [1:0] muxb_ctl_i,
+ input [2:0] pc_gen_ctl_i,
+ input [1:0] rd_sel_i,
+ input [0:0] wb_mux_ctl_i,
+ input [0:0] wb_we_i,
+ output [4:0] alu_func_o,
+ output [0:0] alu_we_o,
+ output [2:0] cmp_ctl_o,
+ output [3:0] dmem_ctl_o,
+ output [3:0] dmem_ctl_ur_o,
+ output [2:0] ext_ctl,
+ output [1:0] muxa_ctl_o,
+ output [1:0] muxb_ctl_o,
+ output [2:0] pc_gen_ctl_o,
+ output [1:0] rd_sel_o,
+ output [0:0] wb_mux_ctl_o,
+ output [0:0] wb_we_o
+ ) ;
wire NET7643;
wire [0:0] BUS4987;
@@ -1501,52 +1470,28 @@
endmodule
module decode_pipe
- (
- pause,
- clk,id2ra_ctl_clr,id2ra_ctl_cls,
- ra2ex_ctl_clr,ins_i,alu_func_o,alu_we_o,
- cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,ext_ctl_o,
- fsm_dly,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,
- wb_mux_ctl_o,wb_we_o
- ) ;
-input pause;
- input clk;
- wire clk;
- input id2ra_ctl_clr;
- wire id2ra_ctl_clr;
- input id2ra_ctl_cls;
- wire id2ra_ctl_cls;
- input ra2ex_ctl_clr;
- wire ra2ex_ctl_clr;
- input [31:0] ins_i;
- wire [31:0] ins_i;
- output [4:0] alu_func_o;
- wire [4:0] alu_func_o;
- output [0:0] alu_we_o;
- wire [0:0] alu_we_o;
- output [2:0] cmp_ctl_o;
- wire [2:0] cmp_ctl_o;
- output [3:0] dmem_ctl_o;
- wire [3:0] dmem_ctl_o;
- output [3:0] dmem_ctl_ur_o;
- wire [3:0] dmem_ctl_ur_o;
- output [2:0] ext_ctl_o;
- wire [2:0] ext_ctl_o;
- output [2:0] fsm_dly;
- wire [2:0] fsm_dly;
- output [1:0] muxa_ctl_o;
- wire [1:0] muxa_ctl_o;
- output [1:0] muxb_ctl_o;
- wire [1:0] muxb_ctl_o;
- output [2:0] pc_gen_ctl_o;
- wire [2:0] pc_gen_ctl_o;
- output [1:0] rd_sel_o;
- wire [1:0] rd_sel_o;
- output [0:0] wb_mux_ctl_o;
- wire [0:0] wb_mux_ctl_o;
- output [0:0] wb_we_o;
- wire [0:0] wb_we_o;
+ (
+ input pause,
+ input clk,
+ input id2ra_ctl_clr,
+ input id2ra_ctl_cls,
+ input ra2ex_ctl_clr,
+ input [31:0] ins_i,
+ output [4:0] alu_func_o,
+ output [0:0] alu_we_o,
+ output [2:0] cmp_ctl_o,
+ output [3:0] dmem_ctl_o,
+ output [3:0] dmem_ctl_ur_o,
+ output [2:0] ext_ctl_o,
+ output [2:0] fsm_dly,
+ output [1:0] muxa_ctl_o,
+ output [1:0] muxb_ctl_o,
+ output [2:0] pc_gen_ctl_o,
+ output [1:0] rd_sel_o,
+ output [0:0] wb_mux_ctl_o,
+ output [0:0] wb_we_o
+) ;
wire [4:0] BUS2040;
wire [0:0] BUS2048;
@@ -1600,8 +1545,6 @@
.ext_ctl(ext_ctl_o),
.ext_ctl_i(BUS2072),
-
-
.muxa_ctl_i(BUS2086),
.muxa_ctl_o(muxa_ctl_o),
.muxb_ctl_i(BUS2094),
@@ -1616,8 +1559,6 @@
.wb_we_o(wb_we_o)
);
-
-
endmodule
1.11 mips789/rtl/verilog/ctl_fsm.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/ctl_fsm.v.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ctl_fsm.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/ctl_fsm.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- ctl_fsm.v 16 Mar 2008 05:31:18 -0000 1.10
+++ ctl_fsm.v 23 Mar 2008 01:27:00 -0000 1.11
@@ -60,9 +60,9 @@
default : delay_counter <=0;
endcase
-/////////////////////////////////////////////////////////
-// Finite State Machine
-//
+ /////////////////////////////////////////////////////////
+ // Finite State Machine
+ //
/*Finite State Machine part1*/
always @ (posedge clk)
if (~rst) CurrState <= `RST;
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