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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat Mar 22 13:40:50 CET 2008
Subject: [cvs-checkins] MODIFIED: usbhostslave ...
Date: 00/08/03 22:13:40 Modified: usbhostslave/RTL/serialInterfaceEngine readUSBWireData.v
Log:
Revision 1.3 - Fixed input metastability and delay hazard issue
Revision Changes Path
1.7 usbhostslave/RTL/serialInterfaceEngine/readUSBWireData.v
http://www.opencores.org/cvsweb.shtml/usbhostslave/RTL/serialInterfaceEngine/readUSBWireData.v.diff?r1=1.6&r2=1.7
(In the diff below, changes in quantity of whitespace are not shown.)
Index: readUSBWireData.v
===================================================================
RCS file: /cvsroot/sfielding/usbhostslave/RTL/serialInterfaceEngine/readUSBWireData.v,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -b -r1.6 -r1.7
--- readUSBWireData.v 14 Oct 2006 04:04:11 -0000 1.6
+++ readUSBWireData.v 22 Mar 2008 12:40:49 -0000 1.7
@@ -115,12 +115,20 @@
reg RxWireEdgeDetect;
reg RxWireActiveReg;
reg RxWireActiveReg2;
+reg [1:0] RxBitsInSyncReg1;
+reg [1:0] RxBitsInSyncReg2;
// buffer output state machine state codes:
`define WAIT_BUFFER_NOT_EMPTY 2'b00
`define WAIT_SIE_RX_READY 2'b01
`define SIE_RX_WRITE 2'b10
+// re-synchronize incoming bits
+always @(posedge clk) begin
+ RxBitsInSyncReg1 <= RxBitsIn;
+ RxBitsInSyncReg2 <= RxBitsInSyncReg1;
+end
+
reg [1:0] bufferOutStMachCurrState;
@@ -158,10 +166,10 @@
end
else begin
RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
- RxBitsInReg <= RxBitsIn;
+ RxBitsInReg <= RxBitsInSyncReg2;
oldRxBitsIn <= RxBitsInReg;
incBufferCnt <= 1'b0; //default value
- if ( (TxWireActiveDrive == 1'b0) && (RxBitsIn != RxBitsInReg)) begin //if edge detected then
+ if ( (TxWireActiveDrive == 1'b0) && (RxBitsInSyncReg2 != RxBitsInReg)) begin //if edge detected then
sampleCnt <= 5'b00000;
RxWireEdgeDetect <= 1'b1; // flag receive activity
RxWireActiveReg <= 1'b1;
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