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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Mar 17 00:05:34 CET 2008
Subject: [cvs-checkins] MODIFIED: r2000 ...
Date: 00/08/03 17:00:05 Modified: r2000/r2000pl/sim/rtl_sim/bin r2000pl.do
Log:
- when freeze or stall; don't let memory operations
- Modification on the CP0
- The CP0 is deplaced in the WB stage
- The INT, SI event signals are treated asynchronously in the WB stage
- The rCAUSE register is asynchronous now
- The wException signal is asyncronous instantanously
- Add a repeat/continous treatement (not completed yet)
- *** The "INT EXCEPTION NO STALL" work correctly
Revision Changes Path
1.3 r2000/r2000pl/sim/rtl_sim/bin/r2000pl.do
http://www.opencores.org/cvsweb.shtml/r2000/r2000pl/sim/rtl_sim/bin/r2000pl.do.diff?r1=1.2&r2=1.3
(In the diff below, changes in quantity of whitespace are not shown.)
Index: r2000pl.do
===================================================================
RCS file: /cvsroot/ameziti/r2000/r2000pl/sim/rtl_sim/bin/r2000pl.do,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- r2000pl.do 11 Feb 2008 06:45:17 -0000 1.2
+++ r2000pl.do 16 Mar 2008 23:05:34 -0000 1.3
@@ -98,10 +98,11 @@
# Simulate #
# -------- #
# the soc processor
-vsim -t 1ps tb_r2000_soc
+vsim tb_r2000_soc
#do {r2000pl_d-cache.udo}
-do {r2000pl_exception.udo}
+#do {r2000pl_exception.udo}
+do {r2000pl_stall-pipeline.udo}
# The viewer
view wave
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