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From: cvs at opencores.org<cvs@o...>
Date: Mon Mar 17 00:05:33 CET 2008
Subject: [cvs-checkins] MODIFIED: r2000 ...
Date: 00/08/03 17:00:05

Modified: r2000/r2000pl/doc/spec MipsR2000-Pipeline_controler.odg
Log:
- when freeze or stall; don't let memory operations

- Modification on the CP0

- The CP0 is deplaced in the WB stage

- The INT, SI event signals are treated asynchronously in the WB stage

- The rCAUSE register is asynchronous now

- The wException signal is asyncronous instantanously

- Add a repeat/continous treatement (not completed yet)



- *** The "INT EXCEPTION NO STALL" work correctly




Revision Changes Path
1.5 r2000/r2000pl/doc/spec/MipsR2000-Pipeline_controler.odg

http://www.opencores.org/cvsweb.shtml/r2000/r2000pl/doc/spec/MipsR2000-Pipeline_controler.odg?rev=1.5&content-type=text/x-cvsweb-markup

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