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Message
From: cvs at opencores.org<cvs@o...>
Date: Mon Mar 17 00:05:31 CET 2008
Subject: [cvs-checkins] MODIFIED: r2000 ...
Date: 00/08/03 17:00:05 Modified: r2000 release.txt
Log:
- when freeze or stall; don't let memory operations
- Modification on the CP0
- The CP0 is deplaced in the WB stage
- The INT, SI event signals are treated asynchronously in the WB stage
- The rCAUSE register is asynchronous now
- The wException signal is asyncronous instantanously
- Add a repeat/continous treatement (not completed yet)
- *** The "INT EXCEPTION NO STALL" work correctly
Revision Changes Path
1.11 r2000/release.txt
http://www.opencores.org/cvsweb.shtml/r2000/release.txt.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: release.txt
===================================================================
RCS file: /cvsroot/ameziti/r2000/release.txt,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- release.txt 11 Feb 2008 06:44:22 -0000 1.10
+++ release.txt 16 Mar 2008 23:05:31 -0000 1.11
@@ -455,3 +455,18 @@
11-02-2008
- Flush must be on all signals in the pipeline.
+
+02-03-2008
+- Add "WB_EPC" in the Write Back stage
+10-03-2008
+- when freeze or stall; don't let memory operations
+ -
+16-03-2008
+- Modification on the CP0
+ - The CP0 is deplaced in the WB stage
+ - The INT, SI event signals are treated asynchronously in the WB stage
+ - The rCAUSE register is asynchronous now
+ - The wException signal is asyncronous instantanously
+ - Add a repeat/continous treatement (not completed yet)
+
+ - *** The "INT EXCEPTION NO STALL" work correctly
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