|
Message
From: cvs at opencores.org<cvs@o...>
Date: Sun Mar 16 06:31:18 CET 2008
Subject: [cvs-checkins] MODIFIED: mips789 ...
Date: 00/08/03 16:06:31 Modified: mips789/rtl/verilog ulit.v RF_stage.v RF_components.v
mips_uart.v mips_core.v mips789_defs.v mem_module.v
EXEC_stage.v decode_pipe.v ctl_fsm.v
Log:
no message
Revision Changes Path
1.10 mips789/rtl/verilog/ulit.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/ulit.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ulit.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/ulit.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- ulit.v 29 Nov 2007 03:50:36 -0000 1.9
+++ ulit.v 16 Mar 2008 05:31:18 -0000 1.10
@@ -27,7 +27,7 @@
always @(posedge clk )
if (~rst )ins_no=0;
- else if (~is_nop)
+ else if (0==is_nop)
ins_no = 1+ins_no;
endmodule
@@ -140,6 +140,8 @@
module r32_reg_clr_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input clr,input cls);always@(posedge clk)if(clr) r32_o<=0;else if(cls)r32_o<=r32_o;else r32_o<=r32_i;endmodule
+ /*
+
module ext_ctl_reg_clr(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input clr);always@(posedge clk)if(clr)ext_ctl_o<=0;else ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg_clr(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input clr);always@(posedge clk)if(clr)rd_sel_o<=0;else rd_sel_o<=rd_sel_i;endmodule
module cmp_ctl_reg_clr(input[`CMP_CTL_LEN-1:0] cmp_ctl_i,output reg[`CMP_CTL_LEN-1:0] cmp_ctl_o,input clk,input clr);always@(posedge clk)if(clr)cmp_ctl_o<=0;else cmp_ctl_o<=cmp_ctl_i;endmodule
@@ -209,3 +211,4 @@
module r32_reg_cls(input[`R32_LEN-1:0] r32_i,output reg[`R32_LEN-1:0] r32_o,input clk,input cls);always@(posedge clk)if(cls) r32_o<=r32_o;else r32_o<=r32_i;endmodule
+ */
\ No newline at end of file
1.9 mips789/rtl/verilog/RF_stage.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/RF_stage.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: RF_stage.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/RF_stage.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- RF_stage.v 26 Nov 2007 13:46:21 -0000 1.8
+++ RF_stage.v 16 Mar 2008 05:31:18 -0000 1.9
@@ -14,74 +14,40 @@
`include "mips789_defs.v"
module rf_stage (
- clk,irq_i,rst_i,wb_we_i,cmp_ctl_i,
- ext_ctl_i,fw_alu_i,fw_cmp_rs,fw_cmp_rt,
- fw_mem_i,id_cmd,ins_i,irq_addr_i,pc_gen_ctl,
- pc_i,rd_sel_i,wb_addr_i,wb_din_i,zz_spc_i,iack_o,
- id2ra_ctl_clr_o,id2ra_ctl_cls_o,ra2ex_ctl_clr_o,ext_o,
- pc_next,rd_index_o,rs_n_o,rs_o,rt_n_o,rt_o
+ input pause,
+ input clk,
+ input irq_i,
+ input rst_i,
+ input wb_we_i,
+ input [2:0] cmp_ctl_i,
+ input [2:0] ext_ctl_i,
+ input [31:0] fw_alu_i,
+ input [2:0] fw_cmp_rs,
+ input [2:0] fw_cmp_rt,
+ input [31:0] fw_mem_i,
+ input [2:0] id_cmd,
+ input [31:0] ins_i,
+ input [31:0] irq_addr_i,
+ input [2:0] pc_gen_ctl,
+ input [31:0] pc_i,
+ input [1:0] rd_sel_i,
+ input [4:0] wb_addr_i,
+ input [31:0] wb_din_i,
+ input [31:0] zz_spc_i,
+ output iack_o,
+ output id2ra_ctl_clr_o,
+ output id2ra_ctl_cls_o,
+ output ra2ex_ctl_clr_o,
+ output [31:0] ext_o,
+ output [31:0] pc_next,
+ output [4:0] rd_index_o,
+ output [4:0] rs_n_o,
+ output [31:0] rs_o,
+ output [4:0] rt_n_o,
+ output [31:0] rt_o
) ;
- input clk;
- wire clk;
- input irq_i;
- wire irq_i;
- input rst_i;
- wire rst_i;
- input wb_we_i;
- wire wb_we_i;
- input [2:0] cmp_ctl_i;
- wire [2:0] cmp_ctl_i;
- input [2:0] ext_ctl_i;
- wire [2:0] ext_ctl_i;
- input [31:0] fw_alu_i;
- wire [31:0] fw_alu_i;
- input [2:0] fw_cmp_rs;
- wire [2:0] fw_cmp_rs;
- input [2:0] fw_cmp_rt;
- wire [2:0] fw_cmp_rt;
- input [31:0] fw_mem_i;
- wire [31:0] fw_mem_i;
- input [2:0] id_cmd;
- wire [2:0] id_cmd;
- input [31:0] ins_i;
- wire [31:0] ins_i;
- input [31:0] irq_addr_i;
- wire [31:0] irq_addr_i;
- input [2:0] pc_gen_ctl;
- wire [2:0] pc_gen_ctl;
- input [31:0] pc_i;
- wire [31:0] pc_i;
- input [1:0] rd_sel_i;
- wire [1:0] rd_sel_i;
- input [4:0] wb_addr_i;
- wire [4:0] wb_addr_i;
- input [31:0] wb_din_i;
- wire [31:0] wb_din_i;
- input [31:0] zz_spc_i;
- wire [31:0] zz_spc_i;
- output iack_o;
- wire iack_o;
- output id2ra_ctl_clr_o;
- wire id2ra_ctl_clr_o;
- output id2ra_ctl_cls_o;
- wire id2ra_ctl_cls_o;
- output ra2ex_ctl_clr_o;
- wire ra2ex_ctl_clr_o;
- output [31:0] ext_o;
- wire [31:0] ext_o;
- output [31:0] pc_next;
- wire [31:0] pc_next;
- output [4:0] rd_index_o;
- wire [4:0] rd_index_o;
- output [4:0] rs_n_o;
- wire [4:0] rs_n_o;
- output [31:0] rs_o;
- wire [31:0] rs_o;
- output [4:0] rt_n_o;
- wire [4:0] rt_n_o;
- output [31:0] rt_o;
- wire [31:0] rt_o;
+
wire NET6609;
@@ -113,6 +79,7 @@
ctl_FSM MAIN_FSM
(
+ .pause(pause),
.clk(clk),
.iack(iack_o),
.id2ra_ctl_clr(id2ra_ctl_clr_o),
@@ -167,7 +134,7 @@
(
.clk(clk),
.clr(NET6609),
- .cls(NET6658),
+ .cls(NET6658|pause),
.r32_i(ins_i),
.r32_o(BUS2085)
);
@@ -208,7 +175,7 @@
);*/
reg_array reg_bank
- (
+ ( // .pause(pause),
.clock(clk),
.data(wb_din_i),
.qa(BUS6061),
1.10 mips789/rtl/verilog/RF_components.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/RF_components.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: RF_components.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/RF_components.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- RF_components.v 29 Nov 2007 03:50:36 -0000 1.9
+++ RF_components.v 16 Mar 2008 05:31:18 -0000 1.10
@@ -104,10 +104,11 @@
clock,
qa,
qb,
- rd_clk_cls,
+ rd_clk_cls
+// pause
// bank_sel
);
-
+ // input pause;
input [31:0] data;
input [4:0] wraddress;
input [4:0] rdaddress_a;
@@ -135,14 +136,15 @@
end
always@(posedge clock)
+ // if( ~pause )
begin
r_data <=data;
r_wraddress<=wraddress;
r_wren<=wren;
end
- always@(posedge clock)
- if (~rd_clk_cls)
+ always@(posedge clock) // ||( 0==pause )
+ if(( 0==rd_clk_cls ))
begin
r_rdaddress_a <=rdaddress_a;
r_rdaddress_b <=rdaddress_b;
1.9 mips789/rtl/verilog/mips_uart.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_uart.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_uart.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_uart.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- mips_uart.v 29 Nov 2007 03:50:36 -0000 1.8
+++ mips_uart.v 16 Mar 2008 05:31:18 -0000 1.9
@@ -23,31 +23,26 @@
endmodule
module uart0 (
- clk,rst,rxd_ft,ser_rxd,txd_ld,
- din,rxd_rdy,ser_txd,txd_busy,dout) ;
- input clk;
- wire clk;
- input rst;
- wire rst;
- input rxd_ft;
- wire rxd_ft;
- input ser_rxd;
- wire ser_rxd;
- input txd_ld;
- wire txd_ld;
- input [7:0] din;
- wire [7:0] din;
- output rxd_rdy;
- wire rxd_rdy;
- output ser_txd;
- wire ser_txd;
- output txd_busy;
- wire txd_busy;
- output [7:0] dout;
- wire [7:0] dout;
+ input clk,
+ input rst,
+ input rxd_ft,
+ input ser_rxd,
+ input txd_ld,
+ input [7:0] din,
+ output rxd_rdy,
+ output ser_txd,
+ output txd_busy,
+ output [7:0] dout
+
+ );
+
+
+
wire clk_uart=clk;
wire w_rxd_rdy;
+
+
integer uart_send;
initial begin
@@ -60,7 +55,11 @@
always @ (txd_ld)
begin
- if (txd_ld) $fwrite( uart_send,"%c",din[7:0]);
+ if (txd_ld)
+ begin
+ $fwrite( uart_send,"%c",din[7:0]);
+ $display("UART0 =>%c<",din[7:0]);
+ end
end
uart_read uart_rd_tak(
1.8 mips789/rtl/verilog/mips_core.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_core.v.diff?r1=1.7&r2=1.8
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_core.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_core.v,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- mips_core.v 18 Nov 2007 03:36:45 -0000 1.7
+++ mips_core.v 16 Mar 2008 05:31:18 -0000 1.8
@@ -14,42 +14,24 @@
`include "mips789_defs.v"
module mips_core (
- clk,irq_i,rst,cop_dout,irq_addr,
- zz_din,zz_ins_i,iack_o,cop_addr_o,
- cop_data_o,cop_mem_ctl_o,zz_addr_o,
- zz_dout,zz_pc_o,zz_wr_en_o
- );
-
- input clk;
- wire clk;
- input irq_i;
- wire irq_i;
- input rst;
- wire rst;
- input [31:0] cop_dout;
- wire [31:0] cop_dout;
- input [31:0] irq_addr;
- wire [31:0] irq_addr;
- input [31:0] zz_din;
- wire [31:0] zz_din;
- input [31:0] zz_ins_i;
- wire [31:0] zz_ins_i;
- output [31:0] zz_addr_o;
- wire [31:0] zz_addr_o;
- output [31:0] zz_dout;
- wire [31:0] zz_dout;
- output [31:0] zz_pc_o;
- wire [31:0] zz_pc_o;
- output [3:0] zz_wr_en_o;
- wire [3:0] zz_wr_en_o;
- output iack_o;
- wire iack_o;
- output [31:0] cop_addr_o;
- wire [31:0] cop_addr_o;
- output [31:0] cop_data_o;
- wire [31:0] cop_data_o;
- output [3:0] cop_mem_ctl_o;
- wire [3:0] cop_mem_ctl_o;
+ input clk,
+ input irq_i,
+ input rst,
+ input [31:0] cop_dout,
+ input [31:0] irq_addr,
+ input [31:0] zz_din,
+ input [31:0] zz_ins_i,
+ output [31:0] zz_addr_o,
+ output [31:0] zz_dout,
+ output [31:0] zz_pc_o,
+ output [3:0] zz_wr_en_o,
+ output iack_o,
+ output [31:0] cop_addr_o,
+ output [31:0] cop_data_o,
+ output [3:0] cop_mem_ctl_o
+
+ );
+
wire NET1375;
@@ -98,6 +80,7 @@
mem_module MEM_CTL
(
+ .pause(0),
.Zz_addr(zz_addr_o),
.Zz_dout(zz_dout),
.Zz_wr_en(zz_wr_en_o),
@@ -113,6 +96,7 @@
rf_stage iRF_stage
(
+ .pause(0),
.clk(clk),
.cmp_ctl_i(BUS109),
.ext_ctl_i(BUS117),
@@ -171,8 +155,9 @@
- r32_reg alu_pass0
+ r32_reg_clr_cls alu_pass0
(
+ .cls(pause),.clr(0),
.clk(clk),
.r32_i(BUS9589),
.r32_o(cop_addr_o)
@@ -180,8 +165,8 @@
- r32_reg alu_pass1
- (
+ r32_reg_clr_cls alu_pass1
+ ( .cls(pause),.clr(0),
.clk(clk),
.r32_i(cop_addr_o),
.r32_o(BUS422)
@@ -198,8 +183,8 @@
- r32_reg cop_data_reg
- (
+ r32_reg_clr_cls cop_data_reg
+ ( .cls(pause),.clr(0),
.clk(clk),
.r32_i(BUS9884),
.r32_o(cop_data_o)
@@ -207,8 +192,10 @@
- r32_reg cop_dout_reg
+ r32_reg_clr_cls cop_dout_reg
(
+ .clr(0),
+ .cls(pause),
.clk(clk),
.r32_i(BUS22401),
.r32_o(BUS7772)
@@ -217,7 +204,7 @@
decode_pipe decoder_pipe
- (
+ ( .pause(0),
.alu_func_o(BUS6275),
.alu_we_o(NET767),
.clk(clk),
@@ -240,8 +227,10 @@
- r32_reg ext_reg
+ r32_reg_clr_cls ext_reg
(
+ .clr(0),
+ .cls(pause),
.clk(clk),
.r32_i(BUS7219),
.r32_o(BUS7231)
@@ -267,8 +256,10 @@
- r32_reg pc
+ r32_reg_clr_cls pc
(
+ .clr(0),
+ .cls(pause),
.clk(clk),
.r32_i(zz_pc_o),
.r32_o(BUS27031)
@@ -276,7 +267,7 @@
- r5_reg rnd_pass0
+ r5_reg_clr_cls rnd_pass0
(
.clk(clk),
.r5_i(BUS775),
@@ -285,8 +276,9 @@
- r5_reg rnd_pass1
- (
+ r5_reg_clr_cls rnd_pass1
+ ( .clr(0),
+ .cls(pause),
.clk(clk),
.r5_i(BUS1726),
.r5_o(BUS1724)
@@ -294,8 +286,9 @@
- r5_reg rnd_pass2
- (
+ r5_reg_clr_cls rnd_pass2
+ ( .clr(0),
+ .cls(pause),
.clk(clk),
.r5_i(BUS1724),
.r5_o(BUS18211)
@@ -303,8 +296,10 @@
- r32_reg rs_reg
+ r32_reg_clr_cls rs_reg
(
+ .clr(0),
+ .cls(pause),
.clk(clk),
.r32_i(BUS24839),
.r32_o(BUS7101)
@@ -312,8 +307,9 @@
- r32_reg rt_reg
- (
+ r32_reg_clr_cls rt_reg
+ ( .clr(0),
+ .cls(pause),
.clk(clk),
.r32_i(BUS7160),
.r32_o(BUS7117)
1.6 mips789/rtl/verilog/mips789_defs.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips789_defs.v.diff?r1=1.5&r2=1.6
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips789_defs.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips789_defs.v,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -b -r1.5 -r1.6
--- mips789_defs.v 29 Nov 2007 03:50:36 -0000 1.5
+++ mips789_defs.v 16 Mar 2008 05:31:18 -0000 1.6
@@ -10,12 +10,15 @@
* Email:mcupro@o... or mcupro@1... *
* *
******************************************************************/
-
`ifndef INCLUDE_H
`define INCLUDE_H
- `define FRQ 50000000
- `define SER_RATE 19200
+
+`timescale 10ns / 1ns
+
+`define FRQ 50000000
+`define SER_RATE 192000 //specialy for simulate in order to make it faster
+
`define FW_ALU 3'b001
`define FW_MEM 3'b010
@@ -105,12 +108,10 @@
`define ALU_MTLO 30
`define ALU_MTHI 31
`define ALU_MULTU 8
-
`define PC_IGN 1
`define PC_KEP 2
`define PC_IRQ 4
`define PC_RST 8
-
`define PC_J 1
`define PC_JR 2
`define PC_BC 4
@@ -118,7 +119,6 @@
`define PC_NOP 0
`define PC_RET 6
`define PC_SPC 6
-
`define RF 13
`define EXEC 10
`define DMEM 4
@@ -179,9 +179,10 @@
`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1)
`define COUNTER_VALUE3 (`COUNTER_VALUE1+3)
- `define DEFAULT_IRQ_ADDR 'H00_00_00_5C
- `define ALTERA
+
+
+//`define ALTERA //this is DEBUG model ,
`else
1.9 mips789/rtl/verilog/mem_module.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mem_module.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mem_module.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mem_module.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- mem_module.v 29 Nov 2007 03:50:36 -0000 1.8
+++ mem_module.v 16 Mar 2008 05:31:18 -0000 1.9
@@ -15,28 +15,19 @@
module mem_module (
- clk,din,dmem_addr_i,dmem_ctl,
- zZ_din,Zz_addr,Zz_dout,Zz_wr_en,dout
+ input pause,
+ input clk,
+ input [31:0] din,
+ input [31:0] dmem_addr_i,
+ input [3:0] dmem_ctl,
+ input [31:0] zZ_din,
+ output [31:0] Zz_addr,
+ output [31:0] Zz_dout,
+ output [3:0] Zz_wr_en,
+ output [31:0] dout
) ;
- input clk;
- wire clk;
- input [31:0] din;
- wire [31:0] din;
- input [31:0] dmem_addr_i;
- wire [31:0] dmem_addr_i;
- input [3:0] dmem_ctl;
- wire [3:0] dmem_ctl;
- input [31:0] zZ_din;
- wire [31:0] zZ_din;
- output [31:0] Zz_addr;
- wire [31:0] Zz_addr;
- output [31:0] Zz_dout;
- wire [31:0] Zz_dout;
- output [3:0] Zz_wr_en;
- wire [3:0] Zz_wr_en;
- output [31:0] dout;
- wire [31:0] dout;
+
wire [3:0] BUS512;
wire [1:0] BUS629;
@@ -44,7 +35,7 @@
infile_dmem_ctl_reg dmem_ctl_post
- (
+ ( .pause(pause),
.byte_addr_o(BUS629),
.clk(clk),
.ctl_i(dmem_ctl),
@@ -90,6 +81,7 @@
module infile_dmem_ctl_reg(
+ input pause,
input clk,
input [3:0]ctl_i,
input [31:0]dmem_addr_i,
@@ -101,6 +93,7 @@
assign byte_addr_i = dmem_addr_i[1:0] ;
always @(posedge clk)
+ if(0==pause)
begin
ctl_o<=(dmem_addr_i[31]==0)?ctl_i:0;
byte_addr_o<=byte_addr_i;
1.11 mips789/rtl/verilog/EXEC_stage.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/EXEC_stage.v.diff?r1=1.10&r2=1.11
(In the diff below, changes in quantity of whitespace are not shown.)
Index: EXEC_stage.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/EXEC_stage.v,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -b -r1.10 -r1.11
--- EXEC_stage.v 29 Nov 2007 03:50:36 -0000 1.10
+++ EXEC_stage.v 16 Mar 2008 05:31:18 -0000 1.11
@@ -14,14 +14,14 @@
`include "mips789_defs.v"
module exec_stage
- (
+ ( pause,
clk,rst,spc_cls_i,alu_func,
dmem_fw_ctl,ext_i,fw_alu,fw_dmem,
muxa_ctl_i,muxa_fw_ctl,muxb_ctl_i,
muxb_fw_ctl,pc_i,rs_i,rt_i,alu_ur_o,
dmem_data_ur_o,zz_spc_o
);
-
+ input pause;
input clk;
wire clk;
input rst;
@@ -91,6 +91,29 @@
.din(rt_i)
);
+ /* alu_muxb1 i_alu_muxb
+ (
+ .b_o(BUS468),
+ .ctl(muxb_ctl_i),
+ .ext(ext_i),
+ .fw_alu(fw_alu),
+ .fw_ctl(muxb_fw_ctl),
+ .fw_mem(fw_dmem),
+ .rt(rt_i)
+ );
+ */
+
+ alu_muxb i_alu_muxb
+ (
+ .b_o(BUS468),
+ .ctl(muxb_ctl_i),
+ .ext(ext_i),
+ // .fw_alu(fw_alu),
+ // .fw_ctl(muxb_fw_ctl),
+ // .fw_mem(fw_dmem),
+ .rt(dmem_data_ur_o)
+ );
+
alu_muxa i_alu_muxa
@@ -108,21 +131,13 @@
- alu_muxb i_alu_muxb
- (
- .b_o(BUS468),
- .ctl(muxb_ctl_i),
- .ext(ext_i),
- .fw_alu(fw_alu),
- .fw_ctl(muxb_fw_ctl),
- .fw_mem(fw_dmem),
- .rt(rt_i)
- );
- r32_reg pc_nxt
+ r32_reg_clr_cls pc_nxt
(
+ .cls(pause),
+ .clr(0),
.clk(clk),
.r32_i(BUS2446),
.r32_o(BUS2332)
@@ -133,7 +148,7 @@
r32_reg_cls spc
(
.clk(clk),
- .cls(spc_cls_i),
+ .cls(spc_cls_i|pause),
.r32_i(pc_i),
.r32_o(zz_spc_o)
);
@@ -173,12 +188,19 @@
.func(ctl)
);
*/
- shifter_tak mips_shifter(
+ /* shifter_ff mips_shifter(
.a(b),
.shift_out(shift_c),
.shift_func(ctl),
.shift_amount(a)
);
+*/ shifter_tak mips_shifter(
+ .a(b),
+ .shift_out(shift_c),
+ .shift_func(ctl),
+ .shift_amount(a)
+ );
+ /* */
alu mips_alu(
@@ -216,16 +238,13 @@
module alu_muxb(
input [31:0] rt,
- input [31:0]fw_alu,
- input [31:0]fw_mem,
input [31:0]ext ,
input [1:0]ctl ,
- input [2:0]fw_ctl ,
output reg [31:0] b_o
);
always@(*)
case (ctl)
- `MUXB_RT :b_o = (fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
+ // `MUXB_RT :b_o =rt; //(fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
`MUXB_EXT : b_o=ext;
default b_o=rt;
endcase
1.10 mips789/rtl/verilog/decode_pipe.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/decode_pipe.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: decode_pipe.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/decode_pipe.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- decode_pipe.v 26 Nov 2007 13:46:21 -0000 1.9
+++ decode_pipe.v 16 Mar 2008 05:31:18 -0000 1.10
@@ -1156,14 +1156,14 @@
-module pipelinedregs (
+module pipelinedregs (pause,
clk,id2ra_ctl_clr,id2ra_ctl_cls,ra2ex_ctl_clr,
alu_func_i,alu_we_i,cmp_ctl_i,dmem_ctl_i,ext_ctl_i,
muxa_ctl_i,muxb_ctl_i,pc_gen_ctl_i,rd_sel_i,wb_mux_ctl_i,
wb_we_i,alu_func_o,alu_we_o,cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,
ext_ctl,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,wb_mux_ctl_o,wb_we_o
) ;
-
+ input pause;
input clk;
wire clk;
input id2ra_ctl_clr;
@@ -1238,7 +1238,7 @@
muxb_ctl_reg_clr_cls U1
(
.clk(clk),
- .clr(id2ra_ctl_clr),
+ .clr(id2ra_ctl_clr|pause),
.cls(id2ra_ctl_cls),
.muxb_ctl_i(muxb_ctl_i),
.muxb_ctl_o(BUS5483)
@@ -1250,7 +1250,7 @@
(
.clk(clk),
.clr(id2ra_ctl_clr),
- .cls(id2ra_ctl_cls),
+ .cls(id2ra_ctl_cls|pause),
.wb_mux_ctl_i(wb_mux_ctl_i),
.wb_mux_ctl_o(BUS5651)
);
@@ -1261,15 +1261,17 @@
(
.clk(clk),
.clr(id2ra_ctl_clr),
- .cls(id2ra_ctl_cls),
+ .cls(id2ra_ctl_cls|pause),
.wb_we_i(wb_we_i),
.wb_we_o(BUS5639)
);
- wb_we_reg U12
+ wb_we_reg_clr_cls U12
(
+ .cls(pause),
+ .clr(0),
.clk(clk),
.wb_we_i(NET7643),
.wb_we_o(wb_we_o)
@@ -1277,8 +1279,9 @@
- wb_mux_ctl_reg_clr U13
+ wb_mux_ctl_reg_clr_cls U13
(
+ .cls(pause),
.clk(clk),
.clr(ra2ex_ctl_clr),
.wb_mux_ctl_i(BUS5651),
@@ -1287,9 +1290,9 @@
- muxb_ctl_reg_clr U14
+ muxb_ctl_reg_clr_cls U14
(
- .clk(clk),
+ .clk(clk),.cls(pause),
.clr(ra2ex_ctl_clr),
.muxb_ctl_i(BUS5483),
.muxb_ctl_o(muxb_ctl_o)
@@ -1297,9 +1300,10 @@
- dmem_ctl_reg_clr U15
+ dmem_ctl_reg_clr_cls U15
(
.clk(clk),
+ .cls(pause),
.clr(ra2ex_ctl_clr),
.dmem_ctl_i(BUS5666),
.dmem_ctl_o(dmem_ctl_ur_o)
@@ -1307,19 +1311,20 @@
- alu_func_reg_clr U16
+ alu_func_reg_clr_cls U16
(
.alu_func_i(BUS5674),
.alu_func_o(alu_func_o),
.clk(clk),
+ .cls(pause),
.clr(ra2ex_ctl_clr)
);
- muxa_ctl_reg_clr U17
+ muxa_ctl_reg_clr_cls U17
(
- .clk(clk),
+ .cls(pause), .clk(clk),
.clr(ra2ex_ctl_clr),
.muxa_ctl_i(BUS5008),
.muxa_ctl_o(muxa_ctl_o)
@@ -1327,18 +1332,19 @@
- wb_mux_ctl_reg U18
+ wb_mux_ctl_reg_clr_cls U18
(
- .clk(clk),
+ .clk(clk), .cls(pause),
+ .clr(0),
.wb_mux_ctl_i(BUS5790),
.wb_mux_ctl_o(wb_mux_ctl_o)
);
- wb_we_reg_clr U19
+ wb_we_reg_clr_cls U19
(
- .clk(clk),
+ .clk(clk),.cls(pause),
.clr(ra2ex_ctl_clr),
.wb_we_i(BUS5639),
.wb_we_o(BUS5682)
@@ -1350,34 +1356,37 @@
(
.clk(clk),
.clr(id2ra_ctl_clr),
- .cls(id2ra_ctl_cls),
+ .cls(id2ra_ctl_cls|pause),
.cmp_ctl_i(cmp_ctl_i),
.cmp_ctl_o(cmp_ctl_o)
);
- wb_we_reg U20
+ wb_we_reg_clr_cls U20
(
- .clk(clk),
+ .clk(clk),.clr(0),.cls(pause),
.wb_we_i(BUS5682),
.wb_we_o(BUS7822)
);
- wb_mux_ctl_reg U21
+ wb_mux_ctl_reg_clr_cls U21
(
.clk(clk),
+ .cls(pause),
+ .clr(0),
.wb_mux_ctl_i(BUS5690),
.wb_mux_ctl_o(BUS5790)
);
- wb_we_reg U22
+ wb_we_reg_clr_cls U22
(
- .clk(clk),
+ .clk(clk), .cls(pause),
+ .clr(0),
.wb_we_i(BUS7299),
.wb_we_o(alu_we_o)
);
@@ -1387,8 +1396,10 @@
assign NET7643 = alu_we_o[0] | BUS7822[0];
- alu_we_reg_clr U24
+ alu_we_reg_clr_cls U24
(
+ .cls(pause),
+
.alu_we_i(BUS4987),
.alu_we_o(BUS7299),
.clk(clk),
@@ -1403,7 +1414,7 @@
.alu_func_o(BUS5674),
.clk(clk),
.clr(id2ra_ctl_clr),
- .cls(id2ra_ctl_cls)
+ .cls(id2ra_ctl_cls|pause)
);
@@ -1412,7 +1423,7 @@
(
.clk(clk),
.clr(id2ra_ctl_clr),
- .cls(id2ra_ctl_cls),
+ .cls(id2ra_ctl_cls|pause),
.dmem_ctl_i(dmem_ctl_i),
.dmem_ctl_o(BUS5666)
);
@@ -1423,7 +1434,7 @@
(
.clk(clk),
.clr(id2ra_ctl_clr),
- .cls(id2ra_ctl_cls),
+ .cls(id2ra_ctl_cls|pause),
.ext_ctl_i(ext_ctl_i),
.ext_ctl_o(ext_ctl)
);
@@ -1434,7 +1445,7 @@
(
.clk(clk),
.clr(id2ra_ctl_clr),
- .cls(id2ra_ctl_cls),
+ .cls(id2ra_ctl_cls|pause),
.rd_sel_i(rd_sel_i),
.rd_sel_o(rd_sel_o)
);
@@ -1447,7 +1458,7 @@
.alu_we_o(BUS4987),
.clk(clk),
.clr(id2ra_ctl_clr),
- .cls(id2ra_ctl_cls)
+ .cls(id2ra_ctl_cls|pause)
);
@@ -1456,7 +1467,7 @@
(
.clk(clk),
.clr(id2ra_ctl_clr),
- .cls(id2ra_ctl_cls),
+ .cls(id2ra_ctl_cls|pause),
.muxa_ctl_i(muxa_ctl_i),
.muxa_ctl_o(BUS5008)
);
@@ -1467,15 +1478,18 @@
(
.clk(clk),
.clr(id2ra_ctl_clr),
- .cls(id2ra_ctl_cls),
+ .cls(id2ra_ctl_cls|pause),
.pc_gen_ctl_i(pc_gen_ctl_i),
.pc_gen_ctl_o(pc_gen_ctl_o)
);
- dmem_ctl_reg U9
+ dmem_ctl_reg_clr_cls U9
(
+
+ .cls(pause),
+ .clr(0),
.clk(clk),
.dmem_ctl_i(dmem_ctl_ur_o),
.dmem_ctl_o(dmem_ctl_o)
@@ -1487,13 +1501,14 @@
module decode_pipe
(
+ pause,
clk,id2ra_ctl_clr,id2ra_ctl_cls,
ra2ex_ctl_clr,ins_i,alu_func_o,alu_we_o,
cmp_ctl_o,dmem_ctl_o,dmem_ctl_ur_o,ext_ctl_o,
fsm_dly,muxa_ctl_o,muxb_ctl_o,pc_gen_ctl_o,rd_sel_o,
wb_mux_ctl_o,wb_we_o
) ;
-
+input pause;
input clk;
wire clk;
input id2ra_ctl_clr;
@@ -1566,6 +1581,11 @@
pipelinedregs pipereg
(
+ .pause(pause),
+ .id2ra_ctl_cls(id2ra_ctl_cls),
+ .id2ra_ctl_clr(id2ra_ctl_clr),
+ .ra2ex_ctl_clr(ra2ex_ctl_clr),
+
.alu_func_i(BUS2040),
.alu_func_o(alu_func_o),
.alu_we_i(BUS2048),
@@ -1578,15 +1598,15 @@
.dmem_ctl_ur_o(dmem_ctl_ur_o),
.ext_ctl(ext_ctl_o),
.ext_ctl_i(BUS2072),
- .id2ra_ctl_clr(id2ra_ctl_clr),
- .id2ra_ctl_cls(id2ra_ctl_cls),
+
+
+
.muxa_ctl_i(BUS2086),
.muxa_ctl_o(muxa_ctl_o),
.muxb_ctl_i(BUS2094),
.muxb_ctl_o(muxb_ctl_o),
.pc_gen_ctl_i(BUS2102),
.pc_gen_ctl_o(pc_gen_ctl_o),
- .ra2ex_ctl_clr(ra2ex_ctl_clr),
.rd_sel_i(BUS2110),
.rd_sel_o(rd_sel_o),
.wb_mux_ctl_i(BUS2118),
1.10 mips789/rtl/verilog/ctl_fsm.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/ctl_fsm.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ctl_fsm.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/ctl_fsm.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- ctl_fsm.v 29 Nov 2007 03:50:36 -0000 1.9
+++ ctl_fsm.v 16 Mar 2008 05:31:18 -0000 1.10
@@ -13,6 +13,7 @@
`include "mips789_defs.v"
module ctl_FSM (
+ input pause,
input clk,
input [2:0] id_cmd,
input irq,
@@ -63,7 +64,10 @@
// Finite State Machine
//
/*Finite State Machine part1*/
- always @ (posedge clk) if (~rst) CurrState <= `RST; else CurrState <= NextState ;
+ always @ (posedge clk)
+ if (~rst) CurrState <= `RST;
+ else if (~pause)
+ CurrState <= NextState ;
always @ (*)/*Finite State Machine part2*/
begin
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