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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Fri Mar 14 16:52:45 CET 2008
    Subject: [cvs-checkins] MODIFIED: System09 ...
    Top
    Date: 00/08/03 14:16:52

    Modified: System09/rtl/System09_Xess_XSA-3S1000
    System09_Xess_XSA-3S1000.ise
    System09_Xess_XSA-3S1000.vhd XSA-3S1000.ucf
    Added: System09/rtl/System09_Xess_XSA-3S1000 xsasdramcntl.vhd
    Log:
    Updated software - XSA-3S1000 now runs FLEX on an IDE drive or CF card.


    Revision Changes Path
    1.2 System09/rtl/System09_Xess_XSA-3S1000/System09_Xess_XSA-3S1000.ise

    http://www.opencores.org/cvsweb.shtml/System09/rtl/System09_Xess_XSA-3S1000/System09_Xess_XSA-3S1000.ise?rev=1.2&content-type=text/x-cvsweb-markup

    <<Binary file>>


    1.2 System09/rtl/System09_Xess_XSA-3S1000/System09_Xess_XSA-3S1000.vhd

    http://www.opencores.org/cvsweb.shtml/System09/rtl/System09_Xess_XSA-3S1000/System09_Xess_XSA-3S1000.vhd.diff?r1=1.1&r2=1.2

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: System09_Xess_XSA-3S1000.vhd
    ===================================================================
    RCS file: /cvsroot/dilbert57/System09/rtl/System09_Xess_XSA-3S1000/System09_Xess_XSA-3S1000.vhd,v
    retrieving revision 1.1
    retrieving revision 1.2
    diff -u -b -r1.1 -r1.2
    --- System09_Xess_XSA-3S1000.vhd 9 Dec 2007 16:06:02 -0000 1.1
    +++ System09_Xess_XSA-3S1000.vhd 14 Mar 2008 15:52:45 -0000 1.2
    @@ -120,18 +120,27 @@
    -- Added IDE Interface for Compact Flash
    -- Replaced KBug9s and stack with Sys09Bug.
    --
    +-- Version 4.0 - 1st February 2008 - John kent
    +-- Replaced Block RAM with SDRAM Interface
    +-- Modified Hold timing for SDRAM
    +-- Added CF and Ethernet interface
    +-- via the 16 bit peripheral bus at $E100
    +--
    --===========================================================================--
    library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use ieee.numeric_std.all;
    +library work;
    + use work.common.all;
    + use WORK.xsasdram.all;
    library unisim;
    use unisim.vcomponents.all;

    entity My_System09 is
    port(
    - Clk100 : in Std_Logic; -- 100MHz Clock input
    + CLKA : in Std_Logic; -- 100MHz Clock input
    SW2_N : in Std_logic; -- Master Reset input (active low)
    SW3_N : in Std_logic; -- Non Maskable Interrupt input (active low)

    @@ -149,25 +158,55 @@
    -- RS232 Port
    RS232_RXD : in Std_Logic;
    RS232_TXD : out Std_Logic;
    --- RS232_DCD : in Std_logic;
    RS232_CTS : in Std_Logic;
    RS232_RTS : out Std_Logic;

    - -- LEDS & Switches
    - STATUS_LED : out std_logic_vector(6 downto 0);
    + -- Status 7 segment LED
    +-- S : out std_logic_vector(7 downto 0);
    +
    + -- SDRAM side
    + SDRAM_clkfb : in std_logic; -- feedback SDRAM clock after PCB delays
    + SDRAM_clkout : out std_logic; -- clock to SDRAM
    + SDRAM_CKE : out std_logic; -- clock-enable to SDRAM
    + SDRAM_CS_N : out std_logic; -- chip-select to SDRAM
    + SDRAM_RAS_N : out std_logic; -- SDRAM row address strobe
    + SDRAM_CAS_N : out std_logic; -- SDRAM column address strobe
    + SDRAM_WE_N : out std_logic; -- SDRAM write enable
    + SDRAM_BA : out std_logic_vector(1 downto 0); -- SDRAM bank address
    + SDRAM_A : out std_logic_vector(12 downto 0); -- SDRAM row/column address
    + SDRAM_D : inout std_logic_vector(15 downto 0); -- data from SDRAM
    + SDRAM_DQMH : out std_logic; -- enable upper-byte of SDRAM databus if true
    + SDRAM_DQML : out std_logic; -- enable lower-byte of SDRAM databus if true
    +
    + -- Peripheral I/O bus $E100 - $E1FF
    + PB_RD_N : out std_logic;
    + PB_WR_N : out std_logic;
    + PB_A : out std_logic_vector(4 downto 0);
    + PB_D : inout std_logic_vector(15 downto 0);

    --- Compact Flash
    --- ide_rst_n : out std_logic;
    + -- IDE Compact Flash $E100 - $E13F
    + ide_dmack_n : out std_logic;
    ide_cs0_n : out std_logic;
    ide_cs1_n : out std_logic;
    - ide_ior_n : out std_logic;
    - ide_iow_n : out std_logic;
    --- ide_cs16_n : out std_logic; - ide_a : out std_logic_vector(2 downto 0); - ide_d : inout std_logic_vector(15 downto 0); --- ide_d : inout std_logic_vector(7 downto 0); - ethernet_cs_n : out std_logic + -- Ethernet $E140 - $E17F + ether_cs_n : out std_logic; + ether_aen : out std_logic; -- Ethernet address enable not + ether_bhe_n : out std_logic; -- Ethernet bus high enable + ether_clk : in std_logic; -- Ethernet clock + ether_rdy : in std_logic; -- Ethernet ready + ether_irq : in std_logic; -- Ethernet irq - Shared with BAR6 + + -- Slot 1 $E180 - $E1BF + slot1_cs_n : out std_logic; +-- slot1_irq : in std_logic; + + -- Slot 2 $E1C0 - $E1FF + slot2_cs_n : out std_logic; +-- slot2_irq : in std_logic; + + -- Disable Flash + FLASH_CE_N : out std_logic ); end My_System09; @@ -202,10 +241,10 @@ signal flex_data_out : Std_Logic_Vector(7 downto 0); -- ACIA/UART Interface signals - signal uart_data_out : Std_Logic_Vector(7 downto 0); - signal uart_cs : Std_Logic; - signal uart_irq : Std_Logic; - signal uart_clk : Std_Logic; + signal acia_data_out : Std_Logic_Vector(7 downto 0); + signal acia_cs : Std_Logic; + signal acia_irq : Std_Logic; + signal acia_clk : Std_Logic; signal rxd : Std_Logic; signal txd : Std_Logic; signal DCD_n : Std_Logic; @@ -220,6 +259,7 @@ -- RAM signal ram_cs : std_logic; -- memory chip select signal ram_data_out : std_logic_vector(7 downto 0); + signal ram_hold : std_logic; -- hold off slow accesses -- CPU Interface signals signal cpu_reset : Std_Logic; @@ -235,6 +275,10 @@ signal cpu_data_in : std_logic_vector(7 downto 0); signal cpu_data_out : std_logic_vector(7 downto 0); + -- Dynamic Address Translation + signal dat_cs : std_logic; + signal dat_addr : std_logic_vector(7 downto 0); + -- Video Display Unit signal vdu_cs : std_logic; signal vdu_data_out : std_logic_vector(7 downto 0); @@ -246,29 +290,71 @@ signal timer_data_out : std_logic_vector(7 downto 0); signal timer_cs : std_logic; signal timer_irq : std_logic; - signal timer_out : std_logic; -- trap signal trap_cs : std_logic; signal trap_data_out : std_logic_vector(7 downto 0); signal trap_irq : std_logic; - -- compact flash port - signal ide_data_out : std_logic_vector(7 downto 0); - signal ide_cs : std_logic; - signal ide_ior : std_logic; - signal ide_iow : std_logic; - signal ide_hold : std_logic; - signal ide_release : std_logic; - signal ide_count : std_logic_vector(3 downto 0); - signal ide_hold_state : hold_state_type; + -- Peripheral Bus port + signal pb_data_out : std_logic_vector(7 downto 0); + signal pb_cs : std_logic; -- peripheral bus chip select + signal pb_wru : std_logic; -- upper byte write strobe + signal pb_wrl : std_logic; -- lower byte write strobe + signal pb_rdu : std_logic; -- upper byte read strobe + signal pb_rdl : std_logic; -- lower byte read strobe + signal pb_hold : std_logic; -- hold peripheral bus access + signal pb_release : std_logic; -- release hold of peripheral bus + signal pb_count : std_logic_vector(3 downto 0); -- hold counter + signal pb_hold_state : hold_state_type; + signal pb_wreg : std_logic_vector(7 downto 0); -- lower byte write register + signal pb_rreg : std_logic_vector(7 downto 0); -- lower byte read register + + -- Peripheral chip selects on Peripheral Bus + signal ide_cs : std_logic; -- IDE CF interface + signal ether_cs : std_logic; -- Ethernet interface + signal slot1_cs : std_logic; -- Expansion slot 1 + signal slot2_cs : std_logic; -- Expansion slot 2 + + +-- SDRAM + + constant FREQ : natural := 100_000; -- operating frequency in KHz + constant CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) + constant PIPE_EN : boolean := false; -- if true, enable pipelined read operations + constant MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh + constant MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank + constant DATA_WIDTH : natural := 16; -- host & SDRAM data width + constant NROWS : natural := 8192; -- number of rows in SDRAM array + constant NCOLS : natural := 512; -- number of columns in SDRAM array + constant HADDR_WIDTH : natural := 24; -- host-side address width + constant SADDR_WIDTH : natural := 13; -- SDRAM-side address width + + signal rst_i : std_logic; -- internal reset signal + signal clk_i : std_logic; -- internal master clock signal + signal lock : std_logic; -- SDRAM clock DLL lock indicator + + -- signals that go through the SDRAM host-side interface + signal opBegun : std_logic; -- SDRAM operation started indicator + signal earlyBegun : std_logic; -- SDRAM operation started indicator + signal ramDone : std_logic; -- SDRAM operation complete indicator + signal rdDone : std_logic; -- SDRAM read operation complete indicator + signal wrDone : std_logic; -- SDRAM write operation complete indicator + signal hAddr : std_logic_vector(HADDR_WIDTH-1 downto 0); -- host address bus + signal hDIn : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data to SDRAM + signal hDOut : std_logic_vector(DATA_WIDTH-1 downto 0); -- host-side data from SDRAM + signal hRd : std_logic; -- host-side read control signal + signal hWr : std_logic; -- host-side write control signal + signal rdPending : std_logic; -- read operation pending in SDRAM pipeline + type ram_rd_type is (rd_state0, rd_state1, rd_state2, rd_state3); + type ram_wr_type is (wr_state0, wr_state1, wr_state2, wr_state3, wr_state4); + signal ram_rd_state : ram_rd_type; + signal ram_wr_state : ram_wr_type; -- signal BaudCount : std_logic_vector(5 downto 0); signal CountL : std_logic_vector(23 downto 0); - signal clk_count : std_logic_vector(1 downto 0); - signal Clk50 : std_logic; + signal clk_count : std_logic_vector(0 downto 0); signal Clk25 : std_logic; - signal SysClk : std_logic; -- buffered 50 MHz clock signal pix_clk : std_logic; ----------------------------------------------------------------- @@ -404,7 +490,7 @@ -- Video Display Unit. -- ---------------------------------------- -component vdu8_mono +component vdu8 generic( VDU_CLOCK_FREQUENCY : integer := CPU_Clock_Frequency; -- HZ VGA_CLOCK_FREQUENCY : integer := PIX_Clock_Frequency; -- HZ @@ -421,7 +507,7 @@ ); port( -- control register interface - vdu_clk : in std_logic; -- CPU Clock - 12.5MHz + vdu_clk : in std_logic; -- CPU Clock - 25MHz vdu_rst : in std_logic; vdu_cs : in std_logic; vdu_rw : in std_logic; @@ -455,9 +541,7 @@ addr : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); - irq : out std_logic; - timer_in : in std_logic; - timer_out : out std_logic + irq : out std_logic ); end component; @@ -481,20 +565,71 @@ ); end component; + ---------------------------------------- -- --- Block RAM program Memory +-- Dynamic Address Translation Registers -- ---------------------------------------- -component ram_32k - Port ( +component dat_ram + port ( clk : in std_logic; rst : in std_logic; cs : in std_logic; rw : in std_logic; - addr : in std_logic_vector (14 downto 0); - rdata : out std_logic_vector (7 downto 0); - wdata : in std_logic_vector (7 downto 0) + addr_lo : in std_logic_vector(3 downto 0); + addr_hi : in std_logic_vector(3 downto 0); + data_in : in std_logic_vector(7 downto 0); + data_out : out std_logic_vector(7 downto 0) + ); +end component; + +component XSASDRAMCntl + generic( + FREQ : natural := FREQ; -- operating frequency in KHz + CLK_DIV : real := CLK_DIV; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) + PIPE_EN : boolean := PIPE_EN; -- if true, enable pipelined read operations + MAX_NOP : natural := MAX_NOP; -- number of NOPs before entering self-refresh + MULTIPLE_ACTIVE_ROWS : boolean := MULTIPLE_ACTIVE_ROWS; -- if true, allow an active row in each bank + DATA_WIDTH : natural := DATA_WIDTH; -- host & SDRAM data width + NROWS : natural := NROWS; -- number of rows in SDRAM array + NCOLS : natural := NCOLS; -- number of columns in SDRAM array + HADDR_WIDTH : natural := HADDR_WIDTH; -- host-side address width + SADDR_WIDTH : natural := SADDR_WIDTH -- SDRAM-side address width + ); + port( + -- host side + clk : in std_logic; -- master clock + bufclk : out std_logic; -- buffered master clock + clk1x : out std_logic; -- host clock sync'ed to master clock (and divided if CLK_DIV>1) + clk2x : out std_logic; -- double-speed host clock + lock : out std_logic; -- true when host clock is locked to master clock + rst : in std_logic; -- reset + rd : in std_logic; -- initiate read operation + wr : in std_logic; -- initiate write operation + earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async) + opBegun : out std_logic; -- read/write/self-refresh op begun (clocked) + rdPending : out std_logic; -- read operation(s) are still in the pipeline + done : out std_logic; -- read or write operation is done + rdDone : out std_logic; -- read done and data is available + hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host + hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host + hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to host + status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM + + -- SDRAM side + sclkfb : in std_logic; -- clock from SDRAM after PCB delays + sclk : out std_logic; -- SDRAM clock sync'ed to master clock + cke : out std_logic; -- clock-enable to SDRAM + cs_n : out std_logic; -- chip-select to SDRAM + ras_n : out std_logic; -- SDRAM row address strobe + cas_n : out std_logic; -- SDRAM column address strobe + we_n : out std_logic; -- SDRAM write enable + ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits + sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address + sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus + dqmh : out std_logic; -- high databits I/O mask + dqml : out std_logic -- low databits I/O mask ); end component; @@ -548,17 +683,17 @@ wdata => cpu_data_out ); -my_uart : ACIA_6850 port map ( +my_acia : ACIA_6850 port map ( clk => cpu_clk, rst => cpu_reset, - cs => uart_cs, + cs => acia_cs, rw => cpu_rw, - irq => uart_irq, + irq => acia_irq, Addr => cpu_addr(0), Datain => cpu_data_out, - DataOut => uart_data_out, - RxC => uart_clk, - TxC => uart_clk, + DataOut => acia_data_out, + RxC => acia_clk, + TxC => acia_clk, RxD => rxd, TxD => txd, DCD_n => dcd_n, @@ -573,8 +708,8 @@ ACIA_Clock_Frequency => ACIA_Clock_Frequency ) port map( - clk => SysClk, - acia_clk => uart_clk + clk => Clk_i, + acia_clk => acia_clk ); ---------------------------------------- @@ -604,7 +739,7 @@ -- Video Display Unit instantiation -- ---------------------------------------- -my_vdu : vdu8_mono +my_vdu : vdu8 generic map( VDU_CLOCK_FREQUENCY => CPU_Clock_Frequency, -- HZ VGA_CLOCK_FREQUENCY => PIX_Clock_Frequency, -- HZ @@ -652,9 +787,7 @@ addr => cpu_addr(0), data_in => cpu_data_out, data_out => timer_data_out, - irq => timer_irq, - timer_in => CountL(5), - timer_out => timer_out + irq => timer_irq ); ---------------------------------------- @@ -674,19 +807,65 @@ irq => trap_irq ); -my_ram : ram_32k port map ( + +my_dat : dat_ram port map ( clk => cpu_clk, rst => cpu_reset, - cs => ram_cs, + cs => dat_cs, rw => cpu_rw, - addr => cpu_addr(14 downto 0), - rdata => ram_data_out, - wdata => cpu_data_out + addr_hi => cpu_addr(15 downto 12), + addr_lo => cpu_addr(3 downto 0), + data_in => cpu_data_out, + data_out => dat_addr(7 downto 0) ); -sys_clk_buffer : BUFG port map( - i => Clk50, - o => SysClk + ------------------------------------------------------------------------ + -- Instantiate the SDRAM controller that connects to the memory tester + -- module and interfaces to the external SDRAM chip. + ------------------------------------------------------------------------ + u1 : xsaSDRAMCntl + generic map( + FREQ => FREQ, + PIPE_EN => PIPE_EN, + DATA_WIDTH => DATA_WIDTH, + MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS, + NROWS => NROWS, + NCOLS => NCOLS, + HADDR_WIDTH => HADDR_WIDTH, + SADDR_WIDTH => SADDR_WIDTH + ) + port map( + -- Host Side + clk => CLKA, -- master clock from external clock source (unbuffered) + bufclk => open, -- buffered master clock output + clk1x => clk_i, -- synchronized master clock (accounts for delays to external SDRAM) + clk2x => open, -- synchronized doubled master clock + lock => lock, -- DLL lock indicator + rst => rst_i, -- reset + rd => hRd, -- host-side SDRAM read control from memory tester + wr => hWr, -- host-side SDRAM write control from memory tester + rdPending => rdPending,-- read operation to SDRAM is in progress + opBegun => opBegun, -- indicates memory read/write has begun + earlyOpBegun => earlyBegun, -- early indicator that memory operation has begun + rdDone => rdDone, -- indicates SDRAM memory read operation is done + done => ramDone, -- indicates SDRAM memory read or write operation is done + hAddr => hAddr, -- host-side address from memory tester to SDRAM + hDIn => hDIn, -- test data pattern from memory tester to SDRAM + hDOut => hDOut, -- SDRAM data output to memory tester + status => open, -- SDRAM controller state (for diagnostics) + -- SDRAM Side + sclkfb => SDRAM_clkfb, -- clock feedback with added external PCB delays + sclk => SDRAM_clkout, -- synchronized clock to external SDRAM + cke => SDRAM_cke, -- SDRAM clock enable + cs_n => SDRAM_cs_n, -- SDRAM chip-select + ras_n => SDRAM_ras_n, -- SDRAM RAS + cas_n => SDRAM_cas_n, -- SDRAM CAS + we_n => SDRAM_we_n, -- SDRAM write-enable + ba => SDRAM_ba, -- SDRAM bank address + sAddr => SDRAM_A, -- SDRAM address + sData => SDRAM_D, -- SDRAM databus + dqmh => SDRAM_dqmh, -- SDRAM DQMH + dqml => SDRAM_dqml -- SDRAM DQML ); cpu_clk_buffer : BUFG port map( @@ -707,216 +886,280 @@ mem_decode: process( cpu_clk, cpu_addr, cpu_rw, cpu_vma, + dat_addr, rom_data_out, flex_data_out, - uart_data_out, + acia_data_out, keyboard_data_out, vdu_data_out, - ide_data_out, + pb_data_out, timer_data_out, trap_data_out, ram_data_out ) begin - case cpu_addr(15 downto 12) is - -- - -- Sys09Bug Monitor ROM $F000 - $FFFF - -- - when "1111" => -- $F800 - $FFFF - cpu_data_in <= rom_data_out; - rom_cs <= cpu_vma; + cpu_data_in <= (others=>'0'); + dat_cs <= '0'; + rom_cs <= '0'; flex_cs <= '0'; - uart_cs <= '0'; + acia_cs <= '0'; keyboard_cs <= '0'; vdu_cs <= '0'; - ide_cs <= '0'; timer_cs <= '0'; trap_cs <= '0'; + pb_cs <= '0'; + ide_cs <= '0'; + ether_cs <= '0'; + slot1_cs <= '0'; + slot2_cs <= '0'; ram_cs <= '0'; + if cpu_addr( 15 downto 8 ) = "11111111" then + cpu_data_in <= rom_data_out; + dat_cs <= cpu_vma; -- write DAT + rom_cs <= cpu_vma; -- read ROM + -- + -- Sys09Bug Monitor ROM $F000 - $FFFF + -- + elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF + cpu_data_in <= rom_data_out; + rom_cs <= cpu_vma; -- -- IO Devices $E000 - $E7FF -- - when "1110" => -- $E000 - $E7FF - rom_cs <= '0'; - flex_cs <= '0'; - ram_cs <= '0'; + elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF + case cpu_addr(11 downto 8) is + -- + -- SWTPC peripherals from $E000 to $E0FF + -- + when "0000" => case cpu_addr(7 downto 4) is -- - -- UART / ACIA $E000 + -- Console Port ACIA $E000 - $E00F -- when "0000" => -- $E000 - cpu_data_in <= uart_data_out; - uart_cs <= cpu_vma; - keyboard_cs <= '0'; - vdu_cs <= '0'; - ide_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; + cpu_data_in <= acia_data_out; + acia_cs <= cpu_vma; -- -- Reserved -- Floppy Disk Controller port $E010 - $E01F -- - when "0001" => -- $E010 - cpu_data_in <= "00000000"; - uart_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - ide_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; -- -- Keyboard port $E020 - $E02F -- when "0010" => -- $E020 cpu_data_in <= keyboard_data_out; - uart_cs <= '0'; keyboard_cs <= cpu_vma; - vdu_cs <= '0'; - ide_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; -- -- VDU port $E030 - $E03F -- when "0011" => -- $E030 cpu_data_in <= vdu_data_out; - uart_cs <= '0'; - keyboard_cs <= '0'; vdu_cs <= cpu_vma; - ide_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; -- - -- Compact Flash $E040 - $E04F + -- Reserved SWTPc MP-T Timer $E040 - $E04F -- when "0100" => -- $E040 - cpu_data_in <= ide_data_out; - uart_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - ide_cs <= cpu_vma; - timer_cs <= '0'; - trap_cs <= '0'; + cpu_data_in <= (others=> '0'); -- -- Timer $E050 - $E05F -- when "0101" => -- $E050 cpu_data_in <= timer_data_out; - uart_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - ide_cs <= '0'; timer_cs <= cpu_vma; - trap_cs <= '0'; -- -- Bus Trap Logic $E060 - $E06F -- when "0110" => -- $E060 cpu_data_in <= trap_data_out; - uart_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - ide_cs <= '0'; - timer_cs <= '0'; trap_cs <= cpu_vma; - when others => -- $E070 to $E7FF - cpu_data_in <= "00000000"; - uart_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - ide_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - end case; + -- + -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F + -- -- - -- Flex RAM $C000 - $DFFF + -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F -- - when "1100" | "1101" => -- $C000 - $DFFF - cpu_data_in <= rom_data_out; - rom_cs <= '0'; + + -- + -- Remaining 6 slots reserved for non SWTPc Peripherals + -- + when others => -- $E0A0 to $E0FF + null; + end case; + -- + -- XST-3.0 Peripheral Bus goes here + -- $E100 to $E1FF + -- Four devices + -- IDE, Ethernet, Slot1, Slot2 + -- + when "0001" => + cpu_data_in <= pb_data_out; + pb_cs <= cpu_vma; + case cpu_addr(7 downto 6) is + -- + -- IDE Interface $E100 to $E13F + -- + when "00" => + ide_cs <= cpu_vma; + -- + -- Ethernet Interface $E140 to $E17F + -- + when "01" => + ether_cs <= cpu_vma; + -- + -- Slot 1 Interface $E180 to $E1BF + -- + when "10" => + slot1_cs <= cpu_vma; + -- + -- Slot 2 Interface $E1C0 to $E1FF + -- + when "11" => + slot2_cs <= cpu_vma; + -- + -- Nothing else + -- + when others => + null; + end case; + -- + -- $E200 to $EFFF reserved for future use + -- + when others => + null; + end case; + -- + -- Flex RAM $0C000 - $0DFFF + -- + elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF + cpu_data_in <= flex_data_out; flex_cs <= cpu_vma; - uart_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - ide_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; - ram_cs <= '0'; -- -- Everything else is RAM -- - when others => + else cpu_data_in <= ram_data_out; - rom_cs <= '0'; - flex_cs <= '0'; - uart_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - ide_cs <= '0'; - timer_cs <= '0'; - trap_cs <= '0'; ram_cs <= cpu_vma; - end case; + end if; end process; -- --- Compact Flash Control +-- 16-bit Peripheral Bus +-- 6809 Big endian +-- ISA bus little endian +-- Not sure about IDE interface -- -compact_flash: process( - cpu_addr, cpu_rw, cpu_vma, cpu_data_out, - ide_cs, ide_ior, ide_iow, ide_d ) -begin --- ide_rst_n <= rst_n; - ide_cs0_n <= not( ide_cs ) or cpu_addr(3); - ide_cs1_n <= not( ide_cs and cpu_addr(3)); --- ide_cs16_n <= '1'; - ide_iow <= ide_cs and (not cpu_rw); - ide_ior <= ide_cs and cpu_rw; - ide_iow_n <= not ide_iow; - ide_ior_n <= not ide_ior; - ide_a <= cpu_addr(2 downto 0); - if ide_iow = '1' then - ide_d(7 downto 0) <= cpu_data_out; +peripheral_bus: process( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out ) +begin + pb_wru <= pb_cs and (not cpu_rw) and (not cpu_addr(0)); + pb_wrl <= pb_cs and (not cpu_rw) and cpu_addr(0) ; + pb_rdu <= pb_cs and cpu_rw and (not cpu_addr(0)); + pb_rdl <= pb_cs and cpu_rw and cpu_addr(0) ; + pb_a <= cpu_addr(5 downto 1); + + -- + -- Register upper byte from CPU on first CPU write + -- and lower byte from the peripheral bus on first CPU read + -- + if cpu_reset = '1' then + pb_wreg <= (others => '0'); + pb_rreg <= (others => '0'); + elsif clk_i'event and clk_i ='1' then + if pb_wru = '1' then + pb_wreg <= cpu_data_out; + end if; + if pb_rdu = '1' then + pb_rreg <= pb_d(7 downto 0); + end if; + end if; + -- + -- Peripheral bus read and write strobes are + -- Syncronized with the 50 MHz clock + -- and are asserted until the peripheral bus hold is released + -- + if cpu_reset = '1' then + pb_wr_n <= '1'; + pb_rd_n <= '1'; + elsif clk_i'event and clk_i ='1' then + if pb_hold = '1' then + pb_wr_n <= not pb_wrl; + pb_rd_n <= not pb_rdu; else - ide_d(7 downto 0) <= "ZZZZZZZZ"; + pb_wr_n <= '1'; + pb_rd_n <= '1'; end if; - ide_data_out <= ide_d(7 downto 0); - ide_d(15 downto 8) <= "ZZZZZZZZ"; + end if; + -- + -- The peripheral bus will be an output + -- the registered even byte on data(15 downto 8) + -- and the CPU odd bytes on data(7 downto 0) + -- on odd byte writes + -- + if pb_wrl = '1' then + pb_d <= pb_wreg & cpu_data_out; + else + pb_d <= (others => 'Z'); + end if; + + -- + -- On even byte reads, + -- the CPU reads the low (even) byte of the peripheral bus + -- On odd byte reads, + -- the CPU reads the registered (odd byte) input from the peripheral bus + -- + if pb_rdu = '1' then + pb_data_out <= pb_d(15 downto 8); + elsif pb_rdl = '1' then + pb_data_out <= pb_rreg; + else + pb_data_out <= (others => '0'); + end if; + end process; -- --- Hold CF access for a few cycles +-- Hold Peripheral bus accesses for a few cycles -- -ide_hold_proc: process( cpu_clk, rst_n ) +peripheral_bus_hold: process( cpu_clk, cpu_reset, pb_rdu, pb_wrl, ether_rdy ) begin - if rst_n = '0' then - ide_release <= '0'; - ide_count <= "0000"; - ide_hold_state <= hold_release_state; - elsif cpu_clk'event and cpu_clk='0' then - case ide_hold_state is + if cpu_reset = '1' then + pb_release <= '0'; + pb_count <= "0000"; + pb_hold_state <= hold_release_state; + elsif cpu_clk'event and cpu_clk='1' then + -- + -- The perpheral bus hold signal should be generated on + -- 16 bit bus read which will be on even byte reads or + -- 16 bit bus write which will be on odd byte writes. + -- + case pb_hold_state is when hold_release_state => - ide_release <= '0'; - if ide_cs = '1' then - ide_count <= "0011"; - ide_hold_state <= hold_request_state; + pb_release <= '0'; + if (pb_rdu = '1') or (pb_wrl = '1') then + pb_count <= "0100"; + pb_hold_state <= hold_request_state; + elsif (pb_rdl = '1') or (pb_wru = '1') then + pb_release <= '1'; + pb_hold_state <= hold_release_state; end if; when hold_request_state => - ide_count <= ide_count - "0001"; - if ide_count = "0000" then - ide_release <= '1'; - ide_hold_state <= hold_release_state; + if pb_count = "0000" then + if ether_rdy = '1' then + pb_release <= '1'; + pb_hold_state <= hold_release_state; + end if; + else + pb_count <= pb_count - "0001"; end if; when others => null; @@ -925,68 +1168,80 @@ end process; -- +-- Compact Flash Control +-- +compact_flash: process( ide_cs, cpu_addr ) +begin + ide_cs0_n <= not( ide_cs ) or cpu_addr(4); + ide_cs1_n <= not( ide_cs and cpu_addr(4)); + ide_dmack_n <= '1'; +end process; + +-- -- Interrupts and other bus control signals -- -interrupts : process( rst_n, - ide_cs, ide_hold, ide_release, - uart_irq, +interrupts : process( lock, rst_n, nmi_n, + pb_cs, pb_hold, pb_release, + ram_cs, ram_hold, + ether_irq, + acia_irq, keyboard_irq, trap_irq, timer_irq ) begin - ide_hold <= ide_cs and (not ide_release); - cpu_reset <= not rst_n; -- CPU reset is active high - cpu_irq <= uart_irq or keyboard_irq; + cpu_reset <= (not rst_n) or (not lock); -- CPU reset is active high + pb_hold <= pb_cs and (not pb_release); + cpu_irq <= acia_irq or keyboard_irq; cpu_nmi <= trap_irq or not( nmi_n ); cpu_firq <= timer_irq; cpu_halt <= '0'; - cpu_hold <= ide_hold; + cpu_hold <= pb_hold or ram_hold; end process; -- -- Flash 7 segment LEDS -- -my_led_flasher: process( SysClk, rst_n, CountL ) +my_led_flasher: process( Clk_i, rst_n, CountL ) begin if rst_n = '0' then CountL <= "000000000000000000000000"; - elsif(SysClk'event and SysClk = '0') then + elsif(Clk_i'event and Clk_i = '1') then CountL <= CountL + 1; end if; - STATUS_LED(6 downto 0) <= CountL(23 downto 17); +-- S(7 downto 0) <= CountL(23 downto 16); end process; -- --- Generate a 50 MHz Clock from 100 MHz +-- Generate a 25 MHz Clock from 50 MHz -- -my_prescaler : process( Clk100, clk_count ) +my_prescaler : process( Clk_i, clk_count ) begin - if Clk100'event and Clk100 = '0' then - clk_count <= clk_count + "01"; + if Clk_i'event and Clk_i = '1' then + clk_count(0) <= not clk_count(0); end if; - Clk50 <= clk_count(0); - Clk25 <= clk_count(1); + Clk25 <= clk_count(0); end process; -- -- Push buttons -- -my_switch_assignments : process( SW2_N, SW3_N ) +my_switch_assignments : process( SW2_N, SW3_N, rst_n ) begin rst_n <= SW2_N; + rst_i <= not rst_n; nmi_n <= SW3_N; -- - -- Disable the ethernet controller + -- Disable Flash memory -- - ethernet_cs_n <= '1'; + FLASH_CE_N <= '1'; end process; -- -- RS232 signals: -- -my_uart_assignments : process( RS232_RXD, RS232_CTS, rxd, rts_n ) +my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n ) begin rxd <= RS232_RXD; cts_n <= RS232_CTS; @@ -996,6 +1251,25 @@ end process; -- +-- Pin assignments for ethernet controller +-- +my_ethernet_assignments : process( clk_i, cpu_reset, ether_cs ) +begin + ether_cs_n <= not ether_cs; + ether_aen <= not ether_cs; -- Ethernet address enable not + ether_bhe_n <= '1'; -- Ethernet bus high enable - 8 bit access only +end process; + +-- +-- I/O expansion slot assignments +-- +my_slot_assignments : process( slot1_cs, slot2_cs) +begin + slot1_cs_n <= not slot1_cs; + slot2_cs_n <= not slot2_cs; +end process; + +-- -- VGA ouputs -- my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o ) @@ -1011,6 +1285,124 @@ VGA_blue(2) <= vga_blue_o; end process; +-- +-- SDRAM assignments +-- +my_sdram_assignments : process( cpu_clk, clk_i, cpu_reset, + opBegun, rdDone, wrDone, + ram_rd_state, ram_wr_state, + cpu_addr, dat_addr, + cpu_data_out, hDout, + ram_cs, cpu_rw, ram_hold ) +begin + if( cpu_reset = '1' ) then + hWr <= '0'; + hRd <= '0'; + wrDone <= '0'; + ram_wr_state <= wr_state0; + ram_rd_state <= rd_state0; + + elsif( clk_i'event and clk_i='0' ) then + -- + -- read state machine + -- + case ram_rd_state is + + when rd_state0 => + if (ram_hold = '1') and (cpu_rw = '1') then + hRd <= '1'; + ram_rd_state <= rd_state1; + end if; + + when rd_state1 => + if opBegun = '1' then + ram_rd_state <= rd_state2; + end if; + + when rd_state2 => + if rdDone = '1' then + hRd <= '0'; + ram_rd_state <= rd_state3; + end if; + + when rd_state3 => + if rdDone = '0' then + ram_rd_state <= rd_state0; + end if; + + when others => + hRd <= '0'; + ram_rd_state <= rd_state0; + end case; + + -- + -- Write state machine + -- + case ram_wr_state is + + when wr_state0 => + if (ram_hold = '1') and (cpu_rw = '0') then + hWr <= '1'; + wrDone <= '0'; + ram_wr_state <= wr_state1; + end if; + + when wr_state1 => + if opBegun = '1' then + hWr <= '0'; + wrDone <= '0'; + ram_wr_state <= wr_state2; + end if; + + when wr_state2 => + hWr <= '0'; + wrDone <= '0'; + ram_wr_state <= wr_state3; + + when wr_state3 => + hWr <= '0'; + wrDone <= '1'; + ram_wr_state <= wr_state4; + + when wr_state4 => + hWr <= '0'; + wrDone <= '0'; + ram_wr_state <= wr_state0; + + when others => + hWr <= '0'; + wrDone <= '0'; + ram_wr_state <= wr_state0; + + end case; + + end if; + -- + -- Strobe host RD and WR signals high on RAM select + -- Return low when cycle has started + -- + if( cpu_reset = '1' ) then + ram_hold <= '0'; + elsif( cpu_clk'event and cpu_clk='1' ) then + -- + -- Hold is intitiated when the RAM is selected + -- and released when access cycle is complete + -- + if (ram_hold = '0') and (ram_cs = '1') then + ram_hold <= '1'; + elsif (ram_hold = '1') and ((rdDone = '1') or (wrDone = '1')) then + ram_hold <= '0'; + end if; + end if; + + hAddr(23 downto 20) <= "0000"; + hAddr(19 downto 12) <= dat_addr; + hAddr(11 downto 0) <= cpu_addr(11 downto 0); + hDin(7 downto 0) <= cpu_data_out; + hDin(15 downto 8) <= (others => '0'); + ram_data_out <= hDout(7 downto 0); + +end process; end rtl; --===================== End of architecture =======================-- 1.2 System09/rtl/System09_Xess_XSA-3S1000/XSA-3S1000.ucf http://www.opencores.org/cvsweb.shtml/System09/rtl/System09_Xess_XSA-3S1000/XSA-3S1000.ucf.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: XSA-3S1000.ucf =================================================================== RCS file: /cvsroot/dilbert57/System09/rtl/System09_Xess_XSA-3S1000/XSA-3S1000.ucf,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- XSA-3S1000.ucf 9 Dec 2007 16:06:02 -0000 1.1 +++ XSA-3S1000.ucf 14 Mar 2008 15:52:45 -0000 1.2 @@ -1,82 +1,47 @@ +##################################################### +# # XSA-3S1000 Board FPGA pin assignment constraints # +##################################################### +# # Clocks # -#net CLKA loc=T9; # 100MHz -#net CLKB loc=P8; # 50MHz -#net CLKC loc=R9; # ??Mhz -net CLK100 loc=T9; # 100MHz Clock +net CLKA loc=T9 | IOSTANDARD = LVCMOS33 ; # 100MHz +#net CLKB loc=P8 | IOSTANDARD = LVCMOS33 ; # 50MHz +#net CLKC loc=R9 | IOSTANDARD = LVCMOS33 ; # ??Mhz # # Push button switches # -NET SW2_N loc=E11; # active-low pushbutton -NET SW3_N loc=A13; # active-low pushbutton +#NET SW1_3_N loc=K2 | IOSTANDARD = LVCMOS33 ; # Flash Block select +#NET SW1_4_N loc=J4 | IOSTANDARD = LVCMOS33 ; # Flash Block +NET SW2_N loc=E11 | IOSTANDARD = LVCMOS33 ; # active-low pushbutton +NET SW3_N loc=A13 | IOSTANDARD = LVCMOS33 ; # active-low pushbutton # # PS/2 Keyboard -net PS2_CLK loc=B16; -net PS2_DAT loc=E13; -# -# Status LED # -net STATUS_LED<0> loc=M6; -net STATUS_LED<1> loc=M11; -net STATUS_LED<2> loc=N6; -net STATUS_LED<3> loc=R7; -net STATUS_LED<4> loc=P10; -net STATUS_LED<5> loc=T7; -net STATUS_LED<6> loc=R10; +net PS2_CLK loc=B16 | IOSTANDARD = LVCMOS33 ; +net PS2_DAT loc=E13 | IOSTANDARD = LVCMOS33 ; # # VGA Outputs # -NET VGA_BLUE<0> LOC=C9; -NET VGA_BLUE<1> LOC=E7; -NET VGA_BLUE<2> LOC=D5; -NET VGA_GREEN<0> LOC=A8; -NET VGA_GREEN<1> LOC=A5; -NET VGA_GREEN<2> LOC=C3; -NET VGA_RED<0> LOC=C8; -NET VGA_RED<1> LOC=D6; -NET VGA_RED<2> LOC=B1; -NET VGA_HSYNC_N LOC=B7; -NET VGA_VSYNC_N LOC=D8; +NET VGA_BLUE<0> LOC=C9 | IOSTANDARD = LVCMOS33 ; +NET VGA_BLUE<1> LOC=E7 | IOSTANDARD = LVCMOS33 ; +NET VGA_BLUE<2> LOC=D5 | IOSTANDARD = LVCMOS33 ; +NET VGA_GREEN<0> LOC=A8 | IOSTANDARD = LVCMOS33 ; +NET VGA_GREEN<1> LOC=A5 | IOSTANDARD = LVCMOS33 ; +NET VGA_GREEN<2> LOC=C3 | IOSTANDARD = LVCMOS33 ; +NET VGA_RED<0> LOC=C8 | IOSTANDARD = LVCMOS33 ; +NET VGA_RED<1> LOC=D6 | IOSTANDARD = LVCMOS33 ; +NET VGA_RED<2> LOC=B1 | IOSTANDARD = LVCMOS33 ; +NET VGA_HSYNC_N LOC=B7 | IOSTANDARD = LVCMOS33 ; +NET VGA_VSYNC_N LOC=D8 | IOSTANDARD = LVCMOS33 ; # -# Flash memory interface -# -#net FLASH_A<0> LOC=N5; -#net FLASH_A<1> LOC=K14; -#net FLASH_A<2> LOC=K13; -#net FLASH_A<3> LOC=K12; -#net FLASH_A<4> LOC=L14; -#net FLASH_A<5> LOC=M16; -#net FLASH_A<6> LOC=L13; -#net FLASH_A<7> LOC=N16; -#net FLASH_A<8> LOC=N14; -#net FLASH_A<9> LOC=P15; -#net FLASH_A<10> LOC=R16; -#net FLASH_A<11> LOC=P14; -#net FLASH_A<12> LOC=P13; -#net FLASH_A<13> LOC=N12; -#net FLASH_A<14> LOC=T14; -#net FLASH_A<15> LOC=R13; -#net FLASH_A<16> LOC=N10; -#net FLASH_A<17> LOC=M14; -#net FLASH_A<18> LOC=K3; -#net FLASH_A<19> LOC=K4; -#net FLASH_D<8> LOC=T4; -#net FLASH_D<9> LOC=R5; -#net FLASH_D<10> LOC=T5; -#net FLASH_D<11> LOC=P6; -#net FLASH_D<12> LOC=M7; -#net FLASH_D<13> LOC=R6; -#net FLASH_D<14> LOC=N7; -#net FLASH_D<15> LOC=P7; -#net FLASH_CE_N LOC=R4; -#net FLASH_OE_N LOC=P5; -#net FLASH_WE_N LOC=M13; -#net FLASH_BYTE_N LOC=T8; -#net FLASH_RDY LOC=L12; -#net FLASH_RST_N LOC=P16; +# Manually assign locations for the DCMs along the bottom of the FPGA +# because PAR sometimes places them in opposing corners and that ruins the clocks. # +INST "u1/dllint" LOC="DCM_X0Y0"; +INST "u1/dllext" LOC="DCM_X1Y0"; + # Manually assign locations for the DCMs along the bottom of the FPGA # because PAR sometimes places them in opposing corners and that ruins the clocks. #INST "u2_dllint" LOC="DCM_X0Y0"; @@ -84,74 +49,153 @@ # # SDRAM memory pin assignments # -#net SDRAM_clkfb loc=N8; # feedback SDRAM clock after PCB delays -#net SDRAM_clkout loc=E10; # clock to SDRAM -#net SDRAM_CKE loc=D7; # SDRAM clock enable -#net SDRAM_CS_N loc=B8; # SDRAM chip-select -#net SDRAM_RAS_N loc=A9; -#net SDRAM_CAS_N loc=A10; -#net SDRAM_WE_N loc=B10; -#net SDRAM_DQMH loc=D9; -#net SDRAM_DQML loc=C10; -#net SDRAM_A<0> loc=B5; -#net SDRAM_A<1> loc=A4; -#net SDRAM_A<2> loc=B4; -#net SDRAM_A<3> loc=E6; -#net SDRAM_A<4> loc=E3; -#net SDRAM_A<5> loc=C1; -#net SDRAM_A<6> loc=E4; -#net SDRAM_A<7> loc=D3; -#net SDRAM_A<8> loc=C2; -#net SDRAM_A<9> loc=A3; -#net SDRAM_A<10> loc=B6; -#net SDRAM_A<11> loc=C5; -#net SDRAM_A<12> loc=C6; -#net SDRAM_D<0> loc=C15; -#net SDRAM_D<1> loc=D12; -#net SDRAM_D<2> loc=A14; -#net SDRAM_D<3> loc=B13; -#net SDRAM_D<4> loc=D11; -#net SDRAM_D<5> loc=A12; -#net SDRAM_D<6> loc=C11; -#net SDRAM_D<7> loc=D10; -#net SDRAM_D<8> loc=B11; -#net SDRAM_D<9> loc=B12; -#net SDRAM_D<10> loc=C12; -#net SDRAM_D<11> loc=B14; -#net SDRAM_D<12> loc=D14; -#net SDRAM_D<13> loc=C16; -#net SDRAM_D<14> loc=F12; -#net SDRAM_D<15> loc=F13; -#net SDRAM_BA<0> loc=A7; -#net SDRAM_BA<1> loc=C7; +net SDRAM_clkfb loc=N8 | IOSTANDARD = LVCMOS33 ; # feedback SDRAM clock after PCB delays +net SDRAM_clkout loc=E10 | IOSTANDARD = LVCMOS33 ; # clock to SDRAM +net SDRAM_CKE loc=D7 | IOSTANDARD = LVCMOS33 ; # SDRAM clock enable +net SDRAM_CS_N loc=B8 | IOSTANDARD = LVCMOS33 ; # SDRAM chip-select +net SDRAM_RAS_N loc=A9 | IOSTANDARD = LVCMOS33 ; +net SDRAM_CAS_N loc=A10 | IOSTANDARD = LVCMOS33 ; +net SDRAM_WE_N loc=B10 | IOSTANDARD = LVCMOS33 ; +net SDRAM_DQMH loc=D9 | IOSTANDARD = LVCMOS33 ; +net SDRAM_DQML loc=C10 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<0> loc=B5 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<1> loc=A4 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<2> loc=B4 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<3> loc=E6 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<4> loc=E3 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<5> loc=C1 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<6> loc=E4 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<7> loc=D3 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<8> loc=C2 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<9> loc=A3 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<10> loc=B6 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<11> loc=C5 | IOSTANDARD = LVCMOS33 ; +net SDRAM_A<12> loc=C6 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<0> loc=C15 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<1> loc=D12 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<2> loc=A14 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<3> loc=B13 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<4> loc=D11 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<5> loc=A12 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<6> loc=C11 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<7> loc=D10 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<8> loc=B11 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<9> loc=B12 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<10> loc=C12 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<11> loc=B14 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<12> loc=D14 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<13> loc=C16 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<14> loc=F12 | IOSTANDARD = LVCMOS33 ; +net SDRAM_D<15> loc=F13 | IOSTANDARD = LVCMOS33 ; +net SDRAM_BA<0> loc=A7 | IOSTANDARD = LVCMOS33 ; +net SDRAM_BA<1> loc=C7 | IOSTANDARD = LVCMOS33 ; +# +# Flash memory interface +# +#net FLASH_A<0> LOC=N5 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<1> LOC=K14 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<2> LOC=K13 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<3> LOC=K12 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<4> LOC=L14 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<5> LOC=M16 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<6> LOC=L13 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<7> LOC=N16 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<8> LOC=N14 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<9> LOC=P15 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<10> LOC=R16 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<11> LOC=P14 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<12> LOC=P13 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<13> LOC=N12 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<14> LOC=T14 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<15> LOC=R13 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<16> LOC=N10 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<17> LOC=M14 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<18> LOC=K3 | IOSTANDARD = LVCMOS33 ; +#net FLASH_A<19> LOC=K4 | IOSTANDARD = LVCMOS33 ; +# +#net FLASH_D<0> LOC=M11 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<1> LOC=N11 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<2> LOC=P10 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<3> LOC=R10 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<4> LOC=T7 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<5> LOC=R7 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<6> LOC=N6 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<7> LOC=M6 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<8> LOC=T4 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<9> LOC=R5 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<10> LOC=T5 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<11> LOC=P6 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<12> LOC=M7 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<13> LOC=R6 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<14> LOC=N7 | IOSTANDARD = LVCMOS33 ; +#net FLASH_D<15> LOC=P7 | IOSTANDARD = LVCMOS33 ; +net FLASH_CE_N LOC=R4 | IOSTANDARD = LVCMOS33 ; +#net FLASH_OE_N LOC=P5 | IOSTANDARD = LVCMOS33 ; +#net FLASH_WE_N LOC=M13 | IOSTANDARD = LVCMOS33 ; +#net FLASH_BYTE_N LOC=T8 | IOSTANDARD = LVCMOS33 ; +#net FLASH_RDY LOC=L12 | IOSTANDARD = LVCMOS33 ; +#net FLASH_RST_N LOC=P16 | IOSTANDARD = LVCMOS33 ; +# +# FPGA Programming interface +# +#net FPGA_D<0> LOC=M11 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D0, S1, LED_C +#net FPGA_D<1> LOC=N11 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D1, S7, LED_DP +#net FPGA_D<2> LOC=P10 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D2, S4, LED_B +#net FPGA_D<3> LOC=R10 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D3, S6, LED_A +#net FPGA_D<4> LOC=T7 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D4, S5, LED_F +#net FPGA_D<5> LOC=R7 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D5, S3, LED_G +#net FPGA_D<6> LOC=N6 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D6, S2, LED_E +#net FPGA_D<7> LOC=M6 | IOSTANDARD = LVCMOS33 ; # shared with FLASH_D7, S0, LED_D +#net FPGA_CCLK LOC=T15 | IOSTANDARD = LVCMOS33 ; +#net FPGA_DONE LOC=R14 | IOSTANDARD = LVCMOS33 ; +#net FPGA_INIT_N LOC=N9 | IOSTANDARD = LVCMOS33 ; +#net FPGA_PROG_N LOC=B3 | IOSTANDARD = LVCMOS33 ; +#net FPGA_TCK LOC=C14 | IOSTANDARD = LVCMOS33 ; +#net FPGA_TDI LOC=A2 | IOSTANDARD = LVCMOS33 ; +#net FPGA_TDI_CSN LOC=R3 | IOSTANDARD = LVCMOS33 ; +#net FPGA_TDO LOC=A15 | IOSTANDARD = LVCMOS33 ; +#net FPGA_TDO_WRN LOC=T3 | IOSTANDARD = LVCMOS33 ; +#net FPGA_TMS LOC=C13 | IOSTANDARD = LVCMOS33 ; +#net FPGA_TMS_BSY LOC=P9 | IOSTANDARD = LVCMOS33 ; +# +# Status LED +# +#net S<0> loc=M6 | IOSTANDARD = LVCMOS33 ; # FPGA_D7, LED_D +#net S<1> loc=M11 | IOSTANDARD = LVCMOS33 ; # FPGA_D0, LED_C +#net S<2> loc=N6 | IOSTANDARD = LVCMOS33 ; # FPGA_D6, LED_E +#net S<3> loc=R7 | IOSTANDARD = LVCMOS33 ; # FPGA_D5, LED_G +#net S<4> loc=P10 | IOSTANDARD = LVCMOS33 ; # FPGA_D2, LED_B +#net S<5> loc=T7 | IOSTANDARD = LVCMOS33 ; # FPGA_D4, LED_F +#net S<6> loc=R10 | IOSTANDARD = LVCMOS33 ; # FPGA_D3, LED_A +#net S<7> loc=N11 | IOSTANDARD = LVCMOS33 ; # FPGA_D1, LED_DP # # Parallel Port # -#net PPORT_load loc=n14; -#net PPORT_clk loc=p15; -#net PPORT_din<0> loc=r16; -#net PPORT_din<1> loc=p14; -#net PPORT_din<2> loc=p13; -#net PPORT_din<3> loc=n12; -#net PPORT_dout<0> loc=n5; -#net PPORT_dout<1> loc=k14; -#net PPORT_dout<2> loc=k13; -#net PPORT_dout<3> loc=t10; -# -# -#net PPORT_d<0> loc=N14; # FLASH_A<8> / PPORT_LOAD -#net PPORT_d<1> loc=P15; # FLASH_A<9> / PPORT_CLK -#net PPORT_d<2> loc=R16; # FLASH_A<10> / PPORT_DIN<0> -#net PPORT_d<3> loc=P14; # FLASH_A<11> / PPORT_DIN<1> -#net PPORT_d<4> loc=P13; # FLASH_A<12> / PPORT_DIN<2> -#net PPORT_d<5> loc=N12; # FLASH_A<13> / PPORT_DIN<3> -## net PPORT_d<6> loc=T14; # FLASH_A<14> -## net PPORT_d<7> loc=R13; # FLASH_A<15> -# -#net PPORT_s<3> loc=N5; # FLASH_A<0> / PPORT_DOUT<0> -#net PPORT_s<4> loc=K14; # FLASH_A<1> / PPORT_DOUT<1> -#net PPORT_s<5> loc=K13; # FLASH_A<2> / PPORT_DOUT<2> -#net PPORT_s<6> loc=T10; # / PPORT_DOUT<3> +#net PPORT_load loc=N14 | IOSTANDARD = LVCMOS33 ; +#net PPORT_clk loc=P15 | IOSTANDARD = LVCMOS33 ; +#net PPORT_din<0> loc=R16 | IOSTANDARD = LVCMOS33 ; +#net PPORT_din<1> loc=P14 | IOSTANDARD = LVCMOS33 ; +#net PPORT_din<2> loc=P13 | IOSTANDARD = LVCMOS33 ; +#net PPORT_din<3> loc=N12 | IOSTANDARD = LVCMOS33 ; +# +#net PPORT_dout<0> loc=N5 | IOSTANDARD = LVCMOS33 ; +#net PPORT_dout<1> loc=K14 | IOSTANDARD = LVCMOS33 ; +#net PPORT_dout<2> loc=K13 | IOSTANDARD = LVCMOS33 ; +#net PPORT_dout<3> loc=T10 | IOSTANDARD = LVCMOS33 ; +# +#net PPORT_d<0> loc=N14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<8> / PPORT_LOAD +#net PPORT_d<1> loc=P15 | IOSTANDARD = LVCMOS33 ; # FLASH_A<9> / PPORT_CLK +#net PPORT_d<2> loc=R16 | IOSTANDARD = LVCMOS33 ; # FLASH_A<10> / PPORT_DIN<0> +#net PPORT_d<3> loc=P14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<11> / PPORT_DIN<1> +#net PPORT_d<4> loc=P13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<12> / PPORT_DIN<2> +#net PPORT_d<5> loc=N12 | IOSTANDARD = LVCMOS33 ; # FLASH_A<13> / PPORT_DIN<3> +##net PPORT_d<6> loc=T14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<14> +##net PPORT_d<7> loc=R13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<15> +# +#net PPORT_s<3> loc=N5 | IOSTANDARD = LVCMOS33 ; # FLASH_A<0> / PPORT_DOUT<0> +#net PPORT_s<4> loc=K14 | IOSTANDARD = LVCMOS33 ; # FLASH_A<1> / PPORT_DOUT<1> +#net PPORT_s<5> loc=K13 | IOSTANDARD = LVCMOS33 ; # FLASH_A<2> / PPORT_DOUT<2> +#net PPORT_s<6> loc=T10 | IOSTANDARD = LVCMOS33 ; # / PPORT_DOUT<3> # ######################################################## # @@ -161,60 +205,122 @@ # # BAR LED # -#net BAR_LED<1> loc=L5; # barled 1 -#net BAR_LED<2> loc=N2; # barled 2 -#net BAR_LED<3> loc=M3; # barled 3 -#net BAR_LED<4> loc=N1; # barled 4 -#net BAR_LED<5> loc=T13; # barled 5 -#net BAR_LED<6> loc=L15; # barled 6 -#net BAR_LED<7> loc=J13; # barled 7 -#net BAR_LED<8> loc=H15; # barled 8 +#net BAR<1> loc=L5 | IOSTANDARD = LVCMOS33 ; # bar led 1, PB_A0 +#net BAR<2> loc=N2 | IOSTANDARD = LVCMOS33 ; # bar led 2, PB_A1 +#net BAR<3> loc=M3 | IOSTANDARD = LVCMOS33 ; # bar led 3, PB_A2 +#net BAR<4> loc=N1 | IOSTANDARD = LVCMOS33 ; # bar led 4, PB_A3 +#net BAR<5> loc=T13 | IOSTANDARD = LVCMOS33 ; # bar led 5, PB_A4 +#net BAR<6> loc=L15 | IOSTANDARD = LVCMOS33 ; # bar led 6, ETHER_IRQ +#net BAR<7> loc=J13 | IOSTANDARD = LVCMOS33 ; # bar led 7, USB_IRQ_N +#net BAR<8> loc=H15 | IOSTANDARD = LVCMOS33 ; # bar led 8, IDE_IRQ +#net BAR<9> loc=J16 | IOSTANDARD = LVCMOS33 ; # bar led 9, SLOT1_IRQ +#net BAR<10> loc=J14 | IOSTANDARD = LVCMOS33 ; # bar led 10, SLOT2_IRQ # # Push Buttons # -#net PB1_N loc=H4; # pushbutton PB1 +#net PB1_N loc=H4 | IOSTANDARD = LVCMOS33 ; # Shared with PB_D15 +#net PB2_N loc=L5 | IOSTANDARD = LVCMOS33 ; # Shared with BAR1, PB_A0 +#net PB3_N loc=N2 | IOSTANDARD = LVCMOS33 ; # Shared with BAR2, PB_A1 +#net PB4_N loc=M3 | IOSTANDARD = LVCMOS33 ; # Shared with BAR3, PB_A2 # # RS232 PORT # -net RS232_TXD loc=J2; # RS232 TD pin 3 -net RS232_RXD loc=G5; # RS232 RD pin 2 -net RS232_CTS loc=D1; # RS232 CTS -net RS232_RTS loc=F4; # RS232 RTS +net RS232_TXD loc=J2 | IOSTANDARD = LVCMOS33 ; # RS232 TD pin 3 +net RS232_RXD loc=G5 | IOSTANDARD = LVCMOS33 ; # RS232 RD pin 2 +net RS232_CTS loc=D1 | IOSTANDARD = LVCMOS33 ; # RS232 CTS +net RS232_RTS loc=F4 | IOSTANDARD = LVCMOS33 ; # RS232 RTS +# +# 16 Bit Peripheral Bus +# +# 5-bit Peripheral address bus +net PB_A<0> loc=L5 | IOSTANDARD = LVCMOS33 ; # Shared with BAR1, PB2 +net PB_A<1> loc=N2 | IOSTANDARD = LVCMOS33 ; # Shared with BAR2, PB3 +net PB_A<2> loc=M3 | IOSTANDARD = LVCMOS33 ; # Shared with BAR3, PB4 +net PB_A<3> loc=N1 | IOSTANDARD = LVCMOS33 ; # Shared with BAR4 +net PB_A<4> loc=T13 | IOSTANDARD = LVCMOS33 ; # Shared with BAR5 +# 16-bit peripheral data bus +net PB_D<0> loc=P12 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW1 +net PB_D<1> loc=J1 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW2 +net PB_D<2> loc=H1 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW3 +net PB_D<3> loc=H3 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW4 +net PB_D<4> loc=G2 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW5 +net PB_D<5> loc=K15 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW6 +net PB_D<6> loc=K16 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW7 +net PB_D<7> loc=F15 | IOSTANDARD = LVCMOS33 ; # Shared with DIPSW8 +net PB_D<8> loc=E2 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_A +net PB_D<9> loc=E1 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_B +net PB_D<10> loc=F3 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_C +net PB_D<11> loc=F2 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_D +net PB_D<12> loc=G4 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_E +net PB_D<13> loc=G3 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_F +net PB_D<14> loc=G1 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_G +net PB_D<15> loc=H4 | IOSTANDARD = LVCMOS33 ; # Shared with LED2_DP, PB1 +net PB_RD_N loc=P2 | IOSTANDARD = LVCMOS33 ; # disk I/O read control +net PB_WR_N loc=R1 | IOSTANDARD = LVCMOS33 ; # disk I/O write control # # IDE Interface # -net IDE_IOR_N loc=P2; # disk I/O read control -net IDE_IOW_N loc=R1; # disk I/O write control -net IDE_CS0_N loc=G15; # disk register-bank select -net IDE_CS1_N loc=G14; # disk register-bank select -net IDE_A<0> loc=L5; # 3-bit disk register address bus -net IDE_A<1> loc=N2; -net IDE_A<2> loc=M3; -net IDE_D<0> loc=P12; # 16-bit disk data bus -net IDE_D<1> loc=J1; -net IDE_D<2> loc=H1; -net IDE_D<3> loc=H3; -net IDE_D<4> loc=G2; -net IDE_D<5> loc=K15; -net IDE_D<6> loc=K16; -net IDE_D<7> loc=F15; -net IDE_D<8> loc=E2; -net IDE_D<9> loc=E1; -net IDE_D<10> loc=F3; -net IDE_D<11> loc=F2; -net IDE_D<12> loc=G4; -net IDE_D<13> loc=G3; -net IDE_D<14> loc=G1; -net IDE_D<15> loc=H4; -#net IDE_IRQ loc=H15; # IDE interrupt -#net IDE_DMACK_N loc=K1; # IDE DMA acknowledge +net IDE_CS0_N loc=G15 | IOSTANDARD = LVCMOS33 ; # disk register-bank select +net IDE_CS1_N loc=G14 | IOSTANDARD = LVCMOS33 ; # disk register-bank select +net IDE_DMACK_N loc=K1 | IOSTANDARD = LVCMOS33 ; # (out) IDE DMA acknowledge +#net IDE_DMARQ loc=L4 | IOSTANDARD = LVCMOS33 ; # (in) IDE DMA request +#net IDE_IORDY loc=L2 | IOSTANDARD = LVCMOS33 ; # (in) IDE IO ready +#net IDE_IRQ loc=H15 | IOSTANDARD = LVCMOS33 ; # (in) IDE interrupt # shared with BAR8 # # Ethernet Controller # Disable if not used # -net ethernet_cs_n loc=G13; # Ethernet chip-enable +net ether_cs_n loc=G13 | IOSTANDARD = LVCMOS33 ; # (out)Ethernet chip-enable +net ether_aen loc=E14 | IOSTANDARD = LVCMOS33 ; # (out) Ethernet address enable not +net ether_bhe_n loc=J3 | IOSTANDARD = LVCMOS33 ; # (out) Ethernet bus high enable +net ether_clk loc=R9 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet clock +net ether_irq loc=L15 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet irq - Shared with BAR6 +net ether_rdy loc=M2 | IOSTANDARD = LVCMOS33 ; # (in) Ethernet ready +# +# Expansion slots +# +net slot1_cs_n loc=E15 | IOSTANDARD = LVCMOS33 ; # (out) +#net slot1_irq loc=J16 | IOSTANDARD = LVCMOS33 ; # (in) Shared with BAR9 +net slot2_cs_n loc=D16 | IOSTANDARD = LVCMOS33 ; # (out) +#net slot2_irq loc=J14 | IOSTANDARD = LVCMOS33 ; # (in) Shared with BAR10 +# +# Audio codec +# +#net audio_lrck loc=R12 | IOSTANDARD = LVCMOS33 ; # (out) +#net audio_mclk loc=P11 | IOSTANDARD = LVCMOS33 ; # (out) +#net audio_sclk loc=T12 | IOSTANDARD = LVCMOS33 ; # (out) +#net audio_sdti loc=M10 | IOSTANDARD = LVCMOS33 ; # (out) +#net audio_sdto loc=K5 | IOSTANDARD = LVCMOS33 ; # (in) +# +# i2c +# +#net i2c_scl loc=F5 | IOSTANDARD = LVCMOS33 ; #(out) +#net i2c_sda loc=D2 | IOSTANDARD = LVCMOS33 ; # (in/out) +# +# USB +# +#NET USB_CLK LOC=M1 | IOSTANDARD = LVCMOS33 ; # (IN) +#NET USB_IRQ_N LOC=J13 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with BAR7 +#NET USB_SUSPEND LOC=l3 | IOSTANDARD = LVCMOS33 ; # (IN) +# +# VIDEO DIGITIZER +# +#NET VIDIN_AVID LOC= | IOSTANDARD = LVCMOS33 ; # (IN) +#NET VIDIN_CLK LOC=H16 | IOSTANDARD = LVCMOS33 ; # (IN) +#NET VIDIN_FID LOC= | IOSTANDARD = LVCMOS33 ; # (IN) +#NET VIDIN_HSYNC LOC= | IOSTANDARD = LVCMOS33 ; # (IN) +#NET VIDIN_IRQ LOC= | IOSTANDARD = LVCMOS33 ; # (IN) +#NET VIDIN_VSYNC LOC= | IOSTANDARD = LVCMOS33 ; # (IN) +#NET VIDIN_Y<0> LOC=H14 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_A +#NET VIDIN_Y<1> LOC=M4 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_B +#NET VIDIN_Y<2> LOC=P1 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_C +#NET VIDIN_Y<3> LOC=N3 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_D +#NET VIDIN_Y<4> LOC=M15 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_E +#NET VIDIN_Y<5> LOC=H13 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_F +#NET VIDIN_Y<6> LOC=G16 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_G +#NET VIDIN_Y<7> LOC=N15 | IOSTANDARD = LVCMOS33 ; # (IN) Shared with LED1_DP # # Timing Constraints # -NET "CLK100" TNM_NET="CLK100"; -TIMESPEC "TS_clk"=PERIOD "CLK100" 10 ns HIGH 50 %; +NET "CLKA" TNM_NET="CLKA"; +TIMESPEC "TS_clk"=PERIOD "CLKA" 10 ns HIGH 50 %; 1.1 System09/rtl/System09_Xess_XSA-3S1000/xsasdramcntl.vhd http://www.opencores.org/cvsweb.shtml/System09/rtl/System09_Xess_XSA-3S1000/xsasdramcntl.vhd?rev=1.1&content-type=text/x-cvsweb-markup Index: xsasdramcntl.vhd =================================================================== -------------------------------------------------------------------- -- Company : XESS Corp. -- Engineer : Dave Vanden Bout -- Creation Date : 05/17/2005 -- Copyright : 2005, XESS Corp -- Tool Versions : WebPACK 6.3.03i -- -- Description: -- Customizes the generic SDRAM controller module for the XSA Board. -- -- Revision: -- 1.1.0 -- -- Additional Comments: -- 1.1.0: -- Added CLK_DIV generic parameter to allow stepping-down the clock frequency. -- Added MULTIPLE_ACTIVE_ROWS generic parameter to enable/disable keeping an active row in each bank. -- 1.0.0: -- Initial release. -- -- License: -- This code can be freely distributed and modified as long as -- this header is not removed. -------------------------------------------------------------------- library IEEE, UNISIM; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use UNISIM.VComponents.all; use WORK.common.all; use WORK.sdram.all; package XSASDRAM is component XSASDRAMCntl generic( FREQ : natural := 100_000; -- operating frequency in KHz CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) PIPE_EN : boolean := false; -- if true, enable pipelined read operations MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank DATA_WIDTH : natural := 16; -- host & SDRAM data width NROWS : natural := 8096; -- number of rows in SDRAM array NCOLS : natural := 512; -- number of columns in SDRAM array HADDR_WIDTH : natural := 24; -- host-side address width SADDR_WIDTH : natural := 13 -- SDRAM-side address width ); port( -- host side clk : in std_logic; -- master clock bufclk : out std_logic; -- buffered master clock clk1x : out std_logic; -- host clock sync'ed to master clock (and divided if CLK_DIV>1) clk2x : out std_logic; -- double-speed host clock lock : out std_logic; -- true when host clock is locked to master clock rst : in std_logic; -- reset rd : in std_logic; -- initiate read operation wr : in std_logic; -- initiate write operation earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async) opBegun : out std_logic; -- read/write/self-refresh op begun (clocked) rdPending : out std_logic; -- read operation(s) are still in the pipeline done : out std_logic; -- read or write operation is done rdDone : out std_logic; -- read done and data is available hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to host status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM -- SDRAM side sclkfb : in std_logic; -- clock from SDRAM after PCB delays sclk : out std_logic; -- SDRAM clock sync'ed to master clock cke : out std_logic; -- clock-enable to SDRAM cs_n : out std_logic; -- chip-select to SDRAM ras_n : out std_logic; -- SDRAM row address strobe cas_n : out std_logic; -- SDRAM column address strobe we_n : out std_logic; -- SDRAM write enable ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus dqmh : out std_logic; -- high databits I/O mask dqml : out std_logic -- low databits I/O mask ); end component; end package XSASDRAM; library IEEE, UNISIM; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use UNISIM.VComponents.all; use WORK.common.all; use WORK.sdram.all; entity XSASDRAMCntl is generic( FREQ : natural := 100_000; -- operating frequency in KHz CLK_DIV : real := 2.0; -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0) PIPE_EN : boolean := false; -- if true, enable pipelined read operations MAX_NOP : natural := 10000; -- number of NOPs before entering self-refresh MULTIPLE_ACTIVE_ROWS : boolean := false; -- if true, allow an active row in each bank DATA_WIDTH : natural := 16; -- host & SDRAM data width NROWS : natural := 8192; -- number of rows in SDRAM array NCOLS : natural := 512; -- number of columns in SDRAM array HADDR_WIDTH : natural := 24; -- host-side address width SADDR_WIDTH : natural := 13 -- SDRAM-side address width ); port( -- host side clk : in std_logic; -- master clock bufclk : out std_logic; -- buffered master clock clk1x : out std_logic; -- host clock sync'ed to master clock (and divided if CLK_DIV>1) clk2x : out std_logic; -- double-speed host clock lock : out std_logic; -- true when host clock is locked to master clock rst : in std_logic; -- reset rd : in std_logic; -- initiate read operation wr : in std_logic; -- initiate write operation earlyOpBegun : out std_logic; -- read/write/self-refresh op begun (async) opBegun : out std_logic; -- read/write/self-refresh op begun (clocked) rdPending : out std_logic; -- read operation(s) are still in the pipeline done : out std_logic; -- read or write operation is done rdDone : out std_logic; -- read done and data is available hAddr : in std_logic_vector(HADDR_WIDTH-1 downto 0); -- address from host hDIn : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from host hDOut : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to host status : out std_logic_vector(3 downto 0); -- diagnostic status of the FSM -- SDRAM side sclkfb : in std_logic; -- clock from SDRAM after PCB delays sclk : out std_logic; -- SDRAM clock sync'ed to master clock cke : out std_logic; -- clock-enable to SDRAM cs_n : out std_logic; -- chip-select to SDRAM ras_n : out std_logic; -- SDRAM row address strobe cas_n : out std_logic; -- SDRAM column address strobe we_n : out std_logic; -- SDRAM write enable ba : out std_logic_vector(1 downto 0); -- SDRAM bank address bits sAddr : out std_logic_vector(SADDR_WIDTH-1 downto 0); -- SDRAM row/column address sData : inout std_logic_vector(DATA_WIDTH-1 downto 0); -- SDRAM in/out databus dqmh : out std_logic; -- high databits I/O mask dqml : out std_logic -- low databits I/O mask ); end XSASDRAMCntl; architecture arch of XSASDRAMCntl is -- The SDRAM controller and external SDRAM chip will clock on the same edge -- if the frequency and divided frequency are both greater than the minimum DLL lock frequency. -- Otherwise the DLLs cannot be used so the SDRAM controller and external SDRAM clock on opposite edges -- to try and mitigate the clock skew between the internal FPGA logic and the external SDRAM. constant MIN_LOCK_FREQ : real := 25_000.0; constant IN_PHASE : boolean := real(FREQ)/CLK_DIV >= MIN_LOCK_FREQ; -- Calculate the frequency of the clock for the SDRAM. constant SDRAM_FREQ : natural := int_select(IN_PHASE, (FREQ*integer(2.0*CLK_DIV))/2, FREQ); -- Compute the CLKDV_DIVIDE generic paramter for the DLL modules. It defaults to 2 when CLK_DIV=1 -- because the DLL does not support a divisor of 1 on the CLKDV output. We use the CLK0 output -- when CLK_DIV=1 so we don't care what is output on thr CLK_DIV output of the DLL. constant CLKDV_DIVIDE : real := real_select(CLK_DIV = 1.0, 2.0, CLK_DIV); signal int_clkin, -- signals for internal logic clock DLL int_clk1x, int_clk1x_b, int_clk2x, int_clk2x_b, int_clkdv, int_clkdv_b : std_logic; signal ext_clkin, sclkfb_b, ext_clk1x : std_logic; -- signals for external logic clock DLL signal dllext_rst, dllext_rst_n : std_logic; -- external DLL reset signal signal clk_i : std_logic; -- clock for SDRAM controller logic signal int_lock, ext_lock, lock_i : std_logic; -- DLL lock signals -- bus for holding output data from SDRAM signal sDOut : std_logic_vector(sData'range); signal sDOutEn : std_logic; begin ----------------------------------------------------------- -- setup the DLLs for clock generation ----------------------------------------------------------- -- master clock must come from a dedicated clock pin clkin : IBUFG port map (I => clk, O => int_clkin); -- The external DLL is driven from the same source as the internal DLL -- if the clock divisor is 1. If CLK_DIV is greater than 1, then the external DLL -- is driven by the divided clock from the internal DLL. Otherwise, the SDRAM will be -- clocked on the opposite edge if the internal and external logic are not in-phase. ext_clkin <= int_clkin when (IN_PHASE and (CLK_DIV = 1.0)) else int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0)) else not int_clkin; -- Generate the DLLs for sync'ing the clocks as long as the clocks -- have a frequency high enough for the DLLs to lock gen_dlls : if IN_PHASE generate -- generate an internal clock sync'ed to the master clock dllint : CLKDLL generic map( CLKDV_DIVIDE => CLKDV_DIVIDE ) port map( CLKIN => int_clkin, CLKFB => int_clk1x_b, CLK0 => int_clk1x, RST => ZERO, CLK90 => open, CLK180 => open, CLK270 => open, CLK2X => int_clk2x, CLKDV => int_clkdv, LOCKED => int_lock ); -- sync'ed single, doubled and divided clocks for use by internal logic int_clk1x_buf : BUFG port map(I => int_clk1x, O => int_clk1x_b); int_clk2x_buf : BUFG port map(I => int_clk2x, O => int_clk2x_b); int_clkdv_buf : BUFG port map(I => int_clkdv, O => int_clkdv_b); -- The external DLL is held in a reset state until the internal DLL locks. -- Then the external DLL reset is released after a delay set by this shift register. -- This keeps the external DLL from locking onto the internal DLL clock signal -- until it is stable. SRL16_inst : SRL16 generic map ( INIT => X"0000" ) port map ( CLK => clk_i, A0 => '1', A1 => '1', A2 => '1', A3 => '1', D => int_lock, Q => dllext_rst_n ); dllext_rst <= not dllext_rst when CLK_DIV/=1.0 else ZERO; -- generate an external SDRAM clock sync'ed to the master clock sclkfb_buf : IBUFG port map(I => sclkfb, O => sclkfb_b); -- SDRAM clock with PCB delays -- sclkfb_buf : BUFGMUX port map(I => sclkfb, O => sclkfb_b); -- SDRAM clock with PCB delays dllext : CLKDLL port map( CLKIN => ext_clkin, -- this is either the master clock or the divided clock from the internal DLL CLKFB => sclkfb_b, CLK0 => ext_clk1x, RST => dllext_rst, CLK90 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLKDV => open, LOCKED => ext_lock ); end generate; -- The buffered clock is just a buffered version of the master clock. bufclk <= int_clkin; -- The host-side clock comes from the CLK0 output of the internal DLL if the clock divisor is 1. -- Otherwise it comes from the CLKDV output if the clock divisor is greater than 1. -- Otherwise it is just a copy of the master clock if the DLLs aren't being used. clk_i <= int_clk1x_b when (IN_PHASE and (CLK_DIV = 1.0)) else int_clkdv_b when (IN_PHASE and (CLK_DIV/=1.0)) else int_clkin; clk1x <= clk_i; -- This is the output of the host-side clock clk2x <= int_clk2x_b when IN_PHASE else int_clkin; -- this is the doubled master clock sclk <= ext_clk1x when IN_PHASE else ext_clkin; -- this is the clock for the external SDRAM -- indicate the lock status of the internal and external DLL lock_i <= int_lock and ext_lock when IN_PHASE else YES; lock <= lock_i; -- lock signal for the host logic -- SDRAM memory controller module u1 : sdramCntl generic map( FREQ => SDRAM_FREQ, IN_PHASE => IN_PHASE, PIPE_EN => PIPE_EN, MAX_NOP => MAX_NOP, MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS, DATA_WIDTH => DATA_WIDTH, NROWS => NROWS, NCOLS => NCOLS, HADDR_WIDTH => HADDR_WIDTH, SADDR_WIDTH => SADDR_WIDTH ) port map( clk => clk_i, -- master clock from external clock source (unbuffered) lock => lock_i, -- valid synchronized clocks indicator rst => rst, -- reset rd => rd, -- host-side SDRAM read control from memory tester wr => wr, -- host-side SDRAM write control from memory tester rdPending => rdPending, opBegun => opBegun, -- SDRAM memory read/write done indicator earlyOpBegun => earlyOpBegun, -- SDRAM memory read/write done indicator rdDone => rdDone, -- SDRAM memory read/write done indicator done => done, hAddr => hAddr, -- host-side address from memory tester hDIn => hDIn, -- test data pattern from memory tester hDOut => hDOut, -- SDRAM data output to memory tester status => status, -- SDRAM controller state (for diagnostics) cke => cke, -- SDRAM clock enable ce_n => cs_n, -- SDRAM chip-select ras_n => ras_n, -- SDRAM RAS cas_n => cas_n, -- SDRAM CAS we_n => we_n, -- SDRAM write-enable ba => ba, -- SDRAM bank address sAddr => sAddr, -- SDRAM address sDIn => sData, -- input data from SDRAM sDOut => sDOut, -- output data to SDRAM sDOutEn => sDOutEn, -- enable drivers to send data to SDRAM dqmh => dqmh, -- SDRAM DQMH dqml => dqml -- SDRAM DQML ); sData <= sDOut when sDOutEn = YES else (others => 'Z'); end arch;

     
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